An FPGA implementation of a neural optimization of block truncation coding for image/video compression

2007 ◽  
Vol 31 (8) ◽  
pp. 477-486 ◽  
Author(s):  
Sherif Saif ◽  
Hazem M. Abbas ◽  
Salwa M. Nassar ◽  
Abdelmonem A. Wahdan
Keyword(s):  
Video Compression ◽  
Fpga Implementation ◽  
Block Truncation Coding ◽  
Neural Optimization

FPGA Implementation of Adaptive Non-linear Predictors for Video Compression

2003 ◽  
pp. 1016-1019
Author(s):  
Rafael Gadea-Girones ◽  
Agustín Ramirez-Agundis ◽  
Joaquín Cerdá-Boluda ◽  
Ricardo Colom-Palero
Keyword(s):  
Video Compression ◽  
Fpga Implementation ◽  
Non Linear ◽  
Linear Predictors

scholarly journals FPGA Implementation of Hardware Architecture for H264/AV Codec Standards

2013 ◽  
Vol 2 (01) ◽  
pp. 01-07
Author(s):  
Prof. Naveen Jain
Keyword(s):  
Wireless Networks ◽  
Discrete Cosine Transform ◽  
Video Compression ◽  
High Throughput ◽  
Low Complexity ◽  
Prediction Equation ◽  
Parallel Process ◽  
Fpga Implementation ◽  
Low Latency ◽  
Efficient Utilization

The proposed work is a modern hardware based architecture for performing transformation, quantisation and prediction is designed which is used for H.264/AVC video standards. This designed hardware find its importance in advanced H264 encoders which are repeatedly find its application in HDTV applications. The H264/AV Codec does video compression and video decompression for prospect broadband and wireless networks.  A low complexity discrete cosine transform is used by DSP embedded multiplier. An intra-prediction equation are employed to get low latency, high throughput, efficient utilization of resources. The proposed architecture also employs both pipeline & parallel process methods. The proposed architecture is implemented using VHDL and synthesised for Virtex 5, and the device is 5vlx50tff665.

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