Impact of technology scaling in SOI back-channel total dose tolerance. A 2-D numerical study using self-consistent oxide code

2000 ◽  
Vol 47 (3) ◽  
pp. 620-626 ◽  
Author(s):  
J.-L. Leray ◽  
P. Paillet ◽  
V. Ferlet-Cavrois ◽  
C. Tavernier ◽  
K. Belhaddad ◽  
...  
Keyword(s):  
Total Dose ◽  
Numerical Study ◽  
Technology Scaling ◽  
Self Consistent ◽  
Impact Of Technology ◽  
Dose Tolerance

Impact of Technology Scaling in sub-100 nm nMOSFETs on Total-Dose Radiation Response and Hot-Carrier Reliability

2014 ◽  
Vol 61 (3) ◽  
pp. 1426-1432 ◽  
Author(s):  
Rajan Arora ◽  
Zachary E. Fleetwood ◽  
En Xia Zhang ◽  
Nelson E. Lourenco ◽  
John D. Cressler ◽  
...  
Keyword(s):  
Total Dose ◽  
Radiation Response ◽  
Technology Scaling ◽  
Hot Carrier ◽  
Impact Of Technology ◽  
Dose Radiation

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

Impact of technology scaling on the performance of domino CMOS logic

2008 ◽  
Author(s):  
Sherif M. Sharroush ◽  
Yasser S. Abdalla ◽  
Ahmed A. Dessouki ◽  
El-Sayed A. El-Badawy
Keyword(s):  
Technology Scaling ◽  
Impact Of Technology

The Impact of Technology Scaling for RF Complementary Metal–Oxide–Semiconductor

2009 ◽  
Vol 48 (1) ◽  
pp. 011208
Author(s):  
Eiji Morifuji ◽  
Hideki Kimijima ◽  
Kenji Kojima ◽  
Masaaki Iwai ◽  
Fumitomo Matsuoka
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Technology Scaling ◽  
Impact Of Technology ◽  
The Impact
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