Stable differential voltage to frequency converter with low supply voltage and frequency offset control

1998 ◽  
Vol 47 (5) ◽  
pp. 1355-1361 ◽  
Author(s):  
D. McDonagh ◽  
K.I. Arshak
Keyword(s):  
Supply Voltage ◽  
Frequency Converter ◽  
Frequency Offset ◽  
Differential Voltage ◽  
Low Supply Voltage

scholarly journals Low Voltage Floating Gate MOS Transistor Based Differential Voltage Squarer

2014 ◽  
Vol 2014 ◽  
pp. 1-6 ◽  
Author(s):  
Maneesha Gupta ◽  
Richa Srivastava ◽  
Urvashi Singh
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Order Effect ◽  
Floating Gate ◽  
Current Output ◽  
Mos Transistor ◽  
Differential Voltage ◽  
Saturation Region ◽  
Linear Differential ◽  
Low Supply Voltage

This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75 V in TSMC 0.18 μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator.

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

1992 ◽  
Vol 27 (4) ◽  
pp. 583-588 ◽  
Author(s):  
Y. Miyawaki ◽  
T. Nakayama ◽  
S. Kobayashi ◽  
N. Ajika ◽  
M. Ohi ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Flash Memories ◽  
Low Supply Voltage

A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Measurement Results ◽  
Voltage Swing ◽  
Current Steering Dac ◽  
Low Supply Voltage

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

scholarly journals DVCC-based Low-power RF Filter with 32 nm CNFETs

2021 ◽  
Author(s):  
Shailendra Tripathi ◽  
Amit Mahesh Joshi
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Satellite Communication ◽  
Supply Voltage ◽  
Wide Band ◽  
Rf Receiver ◽  
Rf Filter ◽  
Low Supply Voltage ◽  
Differential Voltage Current Conveyor ◽  
Carbon Nanotube Fet

Abstract This work presents a wide-band active filter for RF receiver. The design uses Carbon Nanotube-FET (CNFET) based differential voltage current conveyor (DVCC) for the implementation of the proposed filter. The filter is designed to operate Ku-band frequencies (12-18 GHz), which is used in satellite communication. Additionally, CMOS based circuit and CNFET-based circuit for DVCC are compared for the performance evaluation. HSPICE simulations have been carried out to test the design aspects of the circuit. The CNFET-based circuit has better results in terms of 60 % reduction in the power consumption and about six times improvement in the bandwidth. The filter utilizes low supply voltage of 0.9 V and consumes 524 µW only. The proposed filter outperforms the existing CMOS-based designs which suggests its usage for low-power high-frequency analog circuits.

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