Quantum C-V modeling in depletion and inversion: accurate extraction of electrical thickness of gate oxide in deep submicron MOSFETs

2002 ◽  
Vol 49 (5) ◽  
pp. 889-894 ◽  
Author(s):  
Wuyun Quan ◽  
D.M. Kim ◽  
Hi-Deok Lee
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
And Inversion ◽  
Electrical Thickness

ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

2002 ◽  
Author(s):  
Ming-Dou Ker ◽  
Chung-Yu Wu ◽  
Hun-Hsien Chang ◽  
Chien-Chang Huang ◽  
Chau-Neng Wu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron

He plus remote plasma nitridation of ultra-thin gate oxide for deep submicron CMOS technology applications

2001 ◽  
Vol 37 (12) ◽  
pp. 788 ◽  
Author(s):  
Shyh-Fann Ting ◽  
Yean-Kuen Fang ◽  
Chien-Hao Chen ◽  
Chih-Wei Yang ◽  
Mo-Chiun Yu ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Remote Plasma ◽  
Plasma Nitridation ◽  
Technology Applications ◽  
Submicron Cmos ◽  
Thin Gate Oxide

Post-soft-breakdown characteristics of deep submicron NMOSFETs with ultrathin gate oxide

2001 ◽  
Vol 22 (7) ◽  
pp. 348-350 ◽  
Author(s):  
Min-Yu Tsai ◽  
Horng-Chih Lin ◽  
Da-Yuan Lee ◽  
Tiao-Yuan Huang
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
Soft Breakdown

Passive Voltage Contrast Technique for Rapid In-Line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology

1998 ◽  
Author(s):  
Victor Liang ◽  
Harlan Sur ◽  
Subhas Bothra
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Relative Magnitude ◽  
Deep Submicron ◽  
Process Step ◽  
First Case ◽  
Contrast Technique ◽  
Rapid Characterization ◽  
Voltage Contrast

Abstract Three case studies in which the passive voltage contrast technique (PVC) was used in-fab during the development of a 0.25mm ASIC CMOS technology for rapid characterization and failure isolation are presented. The first case involved using the PVC technique to evaluate the gate oxide quality at different points of the process, allowing for quick identification of the process steps that were damaging the gate oxide and the relative magnitude of the damage that each process step contributed. PVC was then used to perform in-line evaluation of the split lots that were ran to address the problem without having to pull wafers off the line for electrical testing. In the second case study, PVC was used in-line to identify the source of siliciderelated gate-to-source/drain leakage. At this point of the process, electrical probing was not possible, and PVC circumvented this problem. The third case involved using PVC to help identify a new failure mechanism for tungsten plug vias that manifested itself due to plasma charging and layout peculiarities related to deep submicron design rules.

Effect of the pre-gate oxide cleaning temperature on the reliability of GOI and devices performances in deep submicron CMOS technology

2008 ◽  
Vol 48 (11-12) ◽  
pp. 1786-1790 ◽  
Author(s):  
Y.T. Chiang ◽  
Y.K. Fang ◽  
Y.J. Huang ◽  
T.H. Chou ◽  
S.Y. Yeh ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Submicron Cmos

Inversion-Channel MOS Devices for Characterization of 4H-SiC/SiO2 Interfaces

2015 ◽  
Vol 821-823 ◽  
pp. 480-483 ◽  
Author(s):  
A.I. Mikhaylov ◽  
Alexey V. Afanasyev ◽  
V.V. Luchinin ◽  
S.A. Reshanov ◽  
Adolf Schöner ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Gate Oxide ◽  
Process Optimisation ◽  
Gate Oxides ◽  
Mos Structure ◽  
Mos Devices ◽  
Inversion Channel ◽  
And Inversion ◽  
Thermally Grown

Electrical properties of the gate oxides thermally grown in N2O on n-type and p-type 4H-SiC have been compared using conventional MOS structure and inversion-channel MOS structure, respectively. Sufficient difference in the electrical properties of the gate oxides grown on n-type and p-type 4H-SiC was revealed. We conclude that the gate oxide process optimisation using inversion-channel MOS devices is superior as compared to the conventional MOS structure.

Thermal Budget for Fabricating a Dual Gate Deep-Submicron CMOS with Thin Pure Gate Oxide

1996 ◽  
Vol 35 (Part 1, No. 2B) ◽  
pp. 1496-1502 ◽  
Author(s):  
Kunihiro Suzuki ◽  
Akira Satoh ◽  
Takayuki Aoyama ◽  
Itaru Namura ◽  
Fumihiko Inoue ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Deep Submicron ◽  
Thermal Budget ◽  
Dual Gate ◽  
Submicron Cmos
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