A novel on-chip electrostatic discharge (ESD) protection with common discharge line for high-speed CMOS LSIs

1997 ◽  
Vol 44 (7) ◽  
pp. 1124-1130 ◽  
Author(s):  
K. Narita ◽  
Y. Horiguchi ◽  
T. Fujii ◽  
K. Nakamura
Keyword(s):  
High Speed ◽  
Electrostatic Discharge ◽  
Discharge Line ◽  
Esd Protection ◽  
On Chip

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

2017 ◽  
Vol 64 (10) ◽  
pp. 3979-3985 ◽  
Author(s):  
Jie-Ting Chen ◽  
Chun-Yu Lin ◽  
Ming-Dou Ker
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Protection Device ◽  
Esd Protection ◽  
On Chip

Employing Ceramic Products to Design an Electrostatic Discharge Protection for High-Speed Signal Lines

2013 ◽  
Vol 389 ◽  
pp. 205-210
Author(s):  
Jing Min Wang ◽  
Chun Ting Lin
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Electrostatic Discharge ◽  
Universal Serial Bus ◽  
Esd Protection ◽  
The Impact ◽  
Real Challenge

With the advance of microelectronics technologies and integrated circuits (ICs) processes, the electrostatic discharge (ESD) has become one of the most important reliability issues in IC products. But treating the ESD-related problems is a real challenge. The paper focuses on the influence of the using of Universal Serial Bus (USB) in plugging and/or unplugging impact arisen from ESD and also proposes an ESD protection design to improve the ESD robustness. This work utilizes off-chip protection along with the commercial ceramic products to achieve effective ESD protection. The impact of the ESD stress applied at the connector pins of USB is evaluated. The protection design for the high-speed signal lines is easily to implement and achieves the following attractive features: (1) Power trace protection, (2) Signals traces protection, (3) GND protection, and (4) Shield protection. Numerous tests have been made to demonstrate the effectiveness of the work.

Self-triggered stacked silicon-controlled rectifier structure (STSSCR) for on-chip electrostatic discharge (ESD) protection

2017 ◽  
Vol 71 ◽  
pp. 1-5 ◽  
Author(s):  
Liu Jizhi ◽  
Qian Lingli ◽  
Tian Rui ◽  
Liu Zhiwei ◽  
Zhao Liu ◽  
...  
Keyword(s):  
Electrostatic Discharge ◽  
Esd Protection ◽  
On Chip

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals On-chip trans-dimensional plasmonic router

Nanophotonics ◽  
2020 ◽  
Vol 9 (10) ◽  
pp. 3357-3365 ◽  
Author(s):  
Shaohua Dong ◽  
Qing Zhang ◽  
Guangtao Cao ◽  
Jincheng Ni ◽  
Ting Shi ◽  
...  
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Incident Angle ◽  
Reciprocal Lattice ◽  
Plasmonic Waveguide ◽  
Optical Diffraction ◽  
Local Dynamic ◽  
Phase Gradient ◽  
On Chip ◽  
Plasmon Polaritons

AbstractPlasmons, as emerging optical diffraction-unlimited information carriers, promise the high-capacity, high-speed, and integrated photonic chips. The on-chip precise manipulations of plasmon in an arbitrary platform, whether two-dimensional (2D) or one-dimensional (1D), appears demanding but non-trivial. Here, we proposed a meta-wall, consisting of specifically designed meta-atoms, that allows the high-efficiency transformation of propagating plasmon polaritons from 2D platforms to 1D plasmonic waveguides, forming the trans-dimensional plasmonic routers. The mechanism to compensate the momentum transformation in the router can be traced via a local dynamic phase gradient of the meta-atom and reciprocal lattice vector. To demonstrate such a scheme, a directional router based on phase-gradient meta-wall is designed to couple 2D SPP to a 1D plasmonic waveguide, while a unidirectional router based on grating metawall is designed to route 2D SPP to the arbitrarily desired direction along the 1D plasmonic waveguide by changing the incident angle of 2D SPP. The on-chip routers of trans-dimensional SPP demonstrated here provide a flexible tool to manipulate propagation of surface plasmon polaritons (SPPs) and may pave the way for designing integrated plasmonic network and devices.

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