A method of eliminating B-mode dielectric breakdown failure in gate oxides utilizing a charging phenomenon

1993 ◽  
Vol 40 (12) ◽  
pp. 2282-2286 ◽  
Author(s):  
T. Ajioka ◽  
A. Nara ◽  
Y. Tominaga ◽  
T. Ushikoshi ◽  
H. Kitabayashi
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxides

The Dielectric Breakdown in Gate Oxides under High Field Stress

2019 ◽  
Vol 19 (2) ◽  
pp. 177-194 ◽  
Author(s):  
Salvatore A. Lombardo ◽  
James H. Stathis ◽  
Gennadi Bersuker
Keyword(s):  
High Field ◽  
Dielectric Breakdown ◽  
Gate Oxides ◽  
Field Stress

Reliability of Gate Oxides on 4H-SiC Epitaxial Surface Planarized by CMP Treatment

2014 ◽  
Vol 778-780 ◽  
pp. 545-548 ◽  
Author(s):  
Keiichi Yamada ◽  
Osamu Ishiyama ◽  
Kentaro Tamura ◽  
Tamotsu Yamashita ◽  
Atsushi Shimozato ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Constant Current ◽  
Wafer Surface ◽  
Gate Oxides ◽  
Mos Capacitor ◽  
Current Time ◽  
Time Dependent Dielectric Breakdown ◽  
High Uniformity ◽  
Current Voltage ◽  
Differential Interference Microscope

This work reports about effect of SiC epitaxial-wafer surface planarization by chemo-mechanical polishing (CMP) treatment on electrical properties of SiC-MOS capacitor. We have observed the surface morphology of 4H-SiC epitaxial layer planarized by CMP treatment using a confocal differential interference microscope, and evaluated the reliability of gate oxides on this surface using constant current time-dependent dielectric breakdown (CC-TDDB) and current-voltage (I-V) characteristics. Surface roughness such as step bunching deteriorates drastically the reliability of gate oxide, while the epitaxial-surface planarization by CMP treatment improved oxide reliability due to the high uniformity of the oxide film thickness.

Influence of Threading Dislocations on Lifetime of Gate Thermal Oxide

2012 ◽  
Vol 717-720 ◽  
pp. 477-480 ◽  
Author(s):  
Kensaku Yamamoto ◽  
M. Nagaya ◽  
H. Watanabe ◽  
E. Okuno ◽  
T. Yamamoto ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Crystal Defects ◽  
Gate Oxides ◽  
Time Dependent Dielectric Breakdown ◽  
Transmission Electron ◽  
Thermal Oxide ◽  
Order Of Magnitude ◽  
The Relationship ◽  
Exact Relationship

The reliability of gate oxides is a fundamental issue for realizing SiC MOSFETs. Many reports said that crystal defects shorten the lifetime of the gate oxide. And, epi defects, the basal plane dislocations and threading screw dislocations (TSD) are considered killer defects. However, because of the high TSD density of commercial SiC wafers, the exact relationship between other kinds of dislocations with lifetime has not been revealed. On the other hand, RAF wafers that we developed have low TSD density, so it is easy to evaluate the relationship between other kinds of dislocations and lifetime. By using RAF wafers, in this study, we clarified the relationship between the lifetime of the gate oxide and crystal defects. We fabricated MOS diodes and measured their lifetimes by TDDB (Time Dependent Dielectric Breakdown) measurement. The breakdown points were defined by the photo-emission method. Finally, we classified the defects by TEM (Transmission Electron Microscopy). As the results, it was clarified that threading edge dislocation (TED) decreases the lifetime as does TSD, which earlier reports said. The lifetime of the gate oxide area, in which a TED is included, was shorter by one order of magnitude than a wear-out breakdown. And, the TSD was two orders.

Correlation between two dielectric breakdown mechanisms in ultra‐thin gate oxides

1996 ◽  
Vol 69 (8) ◽  
pp. 1128-1130 ◽  
Author(s):  
Hideki Satake ◽  
Naoki Yasuda ◽  
Shin‐ichi Takagi ◽  
Akira Toriumi
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxides
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