Interstitial redundancy: an area efficient fault tolerance scheme for large area VLSI processor arrays

1988 ◽  
Vol 37 (11) ◽  
pp. 1398-1410 ◽  
Author(s):  
A.D. Singh
Keyword(s):  
Fault Tolerance ◽  
Large Area ◽  
Processor Arrays ◽  
Area Efficient

Nanoporous gold decorated with silver nanoparticles as large area efficient SERS substrate

2017 ◽  
Author(s):  
Denis Garoli ◽  
Eugenio Calandrini ◽  
Paolo Ponzellini ◽  
Matteo Ardini ◽  
Sandro Cattarin ◽  
...  
Keyword(s):  
Silver Nanoparticles ◽  
Nanoporous Gold ◽  
Sers Substrate ◽  
Large Area ◽  
Area Efficient

scholarly journals Large area efficient interface layer free monolithic perovskite/homo-junction-silicon tandem solar cell with over 20% efficiency

2018 ◽  
Vol 11 (9) ◽  
pp. 2432-2443 ◽  
Author(s):  
Jianghui Zheng ◽  
Cho Fai Jonathan Lau ◽  
Hamid Mehrvarz ◽  
Fa-Jun Ma ◽  
Yajie Jiang ◽  
...  
Keyword(s):  
Solar Cell ◽  
Interface Layer ◽  
Tandem Solar Cell ◽  
Large Area ◽  
Area Efficient

A simple and scalable interface-layer free monolithic perovskite/silicon tandem has been demonstrated achieving over 20% efficiency on a large area.

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

2015 ◽  
Vol 64 (10) ◽  
pp. 2926-2939 ◽  
Author(s):  
Guiyuan Jiang ◽  
Jigang Wu ◽  
Yajun Ha ◽  
Yi Wang ◽  
Jizhou Sun
Keyword(s):  
Fault Tolerance ◽  
Heuristic Algorithms ◽  
Three Dimensional ◽  
Processor Arrays

AFTER: Asynchronous Fault-Tolerant Router Design in Network-on-Chip

2016 ◽  
Vol 25 (06) ◽  
pp. 1650050 ◽  
Author(s):  
Yiming Ouyang ◽  
Qi Chen ◽  
Xiumin Wang ◽  
Xiaoye Ouyang ◽  
Huaguo Liang ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Large Scale ◽  
Fault Tolerant ◽  
Shortest Paths ◽  
Power Saving ◽  
Network On Chip ◽  
Large Area ◽  
Clock Tree ◽  
Tree Distribution ◽  
On Chip

Large scale synchronous network-on-chip (NoC) requires complex clock tree design, which leads to a large area overhead and power consumption. Based on handshaking protocols, asynchronous NoC does not have global clock tree distribution, which results in a natural power saving mode without any explicit clock gating. However, the faults occurring in such asynchronous networks will seriously affect their performances. In this paper, we propose AFTER, an Asynchronous Fault-TolErant Router, which uses the quasi delay insensitive (QDI) logic. The proposed router is able to detect the faults of ports and links. Then, a fault-tolerant routing mechanism, based on the port priority in different quadrants, is proposed to maximize the number of packets that can be transmitted via the shortest paths. In this way, the fault-tolerance of asynchronous routers can be achieved. Besides that, AFTER could also achieve high scalability, and is suitable for the large scale globally asynchronous locally synchronous (GALS) system. The experimental results show that, when faults occur in the network, AFTER has a better fault-tolerance performance than the reference.

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