SIMULATION OF INTERFACE COUPLING EFFECTS IN ULTRA—THIN SILICON ON INSULATOR MOSFET's

1992 ◽  
Vol 11 (4) ◽  
pp. 513-517 ◽  
Author(s):  
A. Hassein—Bey ◽  
S. Cristoloveanu
Keyword(s):  
Silicon On Insulator ◽  
Coupling Effects ◽  
Interface Coupling ◽  
Thin Silicon

Interface coupling effects in thin silicon-on-insulator MOSFET's

1990 ◽  
Vol 8 (1) ◽  
pp. 111-116 ◽  
Author(s):  
T. Ouisse ◽  
S. Cristoloveanu ◽  
T. Elewa ◽  
B. Boukriss ◽  
A. Chovet
Keyword(s):  
Silicon On Insulator ◽  
Coupling Effects ◽  
Interface Coupling ◽  
Thin Silicon

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Formation technology of flat surface with epitaxial growth on ion-implanted (100)-oriented Si surface of thin silicon-on-insulator

2017 ◽  
Vol 56 (10) ◽  
pp. 105503
Author(s):  
Kiichi Furukawa ◽  
Akinobu Teramoto ◽  
Rihito Kuroda ◽  
Tomoyuki Suwa ◽  
Keiichi Hashimoto ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
Flat Surface ◽  
Silicon On Insulator ◽  
Thin Silicon ◽  
Ion Implanted

Fabrication of thin silicon-on-insulator flims using laser recrystallisation

1985 ◽  
Vol 21 (23) ◽  
pp. 1102 ◽  
Author(s):  
J.P. Colinge ◽  
H.K. Hu ◽  
S. Peng
Keyword(s):  
Silicon On Insulator ◽  
Thin Silicon

Diffusion of Silicon Interstitials in thin Silicon Films on Insulator in Neutral and Oxidising Annealing Ambients

1997 ◽  
Vol 469 ◽  
Author(s):  
Guénolé C.M. Silvestre
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Annealing Treatment ◽  
Silicon On Insulator ◽  
Buried Oxide ◽  
Thermal Oxide ◽  
Good Crystalline Quality ◽  
Thin Silicon ◽  
Experimental Values ◽  
Fault Growth

ABSTRACTSilicon-On-Insulator (SOI) materials have emerged as a very promising technology for the fabrication of high performance integrated circuits since they offer significant improvement to device performance. Thin silicon layers of good crystalline quality are now widely available on buried oxide layers of various thicknesses with good insulating properties. However, the SOI structure is quite different from that of bulk silicon. This paper will discuss a study of point-defect diffusion and recombination in thin silicon layers during high temperature annealing treatment through the investigation of stacking-fault growth kinetics. The use of capping layers such as nitride, thin thermal oxide and thick deposited oxide outlines the diffusion mechanisms of interstitials in the SOI structure. It also shows that the buried oxide layer is a very good barrier to the diffusion of point defects and that excess silicon interstitials may be reincorporated at the top interface with the thermal oxide through the formation of SiO species. Finally, from the experimental values of the activation energies for the growth and the shrinkage of stacking-faults, the energy of interstitial creation is evaluated to be 2.6 eV, the energy for interstitial migration to be 1.8 eV and the energy of interstitial generation during oxidation to be 0.2 eV.

Doping Measurements in Thin Silicon‐On‐Insulator Films

1999 ◽  
Vol 146 (7) ◽  
pp. 2737-2743 ◽  
Author(s):  
S. Hénaux ◽  
F. Mondon ◽  
F. Gusella ◽  
I. Kling ◽  
G. Reimbold
Keyword(s):  
Silicon On Insulator ◽  
Thin Silicon
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