scholarly journals Relative acceleration noise mitigation for nanocrystal matter-wave interferometry: Applications to entangling masses via quantum gravity

2021 ◽  
Vol 3 (2) ◽  
Author(s):  
Marko Toroš ◽  
Thomas W. van de Kamp ◽  
Ryan J. Marshman ◽  
M. S. Kim ◽  
Anupam Mazumdar ◽  
...  
2019 ◽  
Author(s):  
Vitaly Kuyukov

Many approaches to quantum gravity consider the revision of the space-time geometry and the structure of elementary particles. One of the main candidates is string theory. It is possible that this theory will be able to describe the problem of hierarchy, provided that there is an appropriate Calabi-Yau geometry. In this paper we will proceed from the traditional view on the structure of elementary particles in the usual four-dimensional space-time. The only condition is that quarks and leptons should have a common emerging structure. When a new formula for the mass of the hierarchy is obtained, this structure arises from topological quantum theory and a suitable choice of dimensional units.


2020 ◽  
Author(s):  
Vitaly Kuyukov
Keyword(s):  

Braking effect in quantum gravity


2019 ◽  
Vol 51 (5) ◽  
Author(s):  
S. Ariwahjoedi ◽  
I. Husin ◽  
I. Sebastian ◽  
F. P. Zen

Nature ◽  
2003 ◽  
Vol 424 (6952) ◽  
pp. 1019-1021 ◽  
Author(s):  
T. Jacobson ◽  
S. Liberati ◽  
D. Mattingly

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.


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