Carrier capture by threading dislocations in (In,Ga)N/GaN heteroepitaxial layers

2010 ◽  
Vol 81 (12) ◽  
Author(s):  
U. Jahn ◽  
O. Brandt ◽  
E. Luna ◽  
X. Sun ◽  
H. Wang ◽  
...  
Keyword(s):  
Threading Dislocations ◽  
Carrier Capture ◽  
Heteroepitaxial Layers

Correlation of Threading Dislocations with the Electron Concentration and Mobility in InN Heteroepitaxial Layers Grown by MBE

2019 ◽  
Vol 9 (1) ◽  
pp. 015006 ◽  
Author(s):  
A. Adikimenakis ◽  
P. Chatzopoulou ◽  
G. P. Dimitrakopulos ◽  
Th. Kehagias ◽  
K. Tsagaraki ◽  
...  
Keyword(s):  
Electron Concentration ◽  
Threading Dislocations ◽  
Heteroepitaxial Layers

High-resolution diffuse x-ray scattering from threading dislocations in heteroepitaxial layers

2004 ◽  
Vol 85 (15) ◽  
pp. 3065-3067 ◽  
Author(s):  
S. Daniš ◽  
V. Holý ◽  
Z. Zhong ◽  
G. Bauer ◽  
O. Ambacher
Keyword(s):  
High Resolution ◽  
Threading Dislocations ◽  
X Ray ◽  
X Ray Scattering ◽  
Heteroepitaxial Layers ◽  
Ray Scattering

A Novel Approach for the Complete Removal of Threading Dislocations from Mismatched Heteroepitaxial Layers

2000 ◽  
Vol 652 ◽  
Author(s):  
X. G. Zhang ◽  
A. Rodriguez ◽  
P. Li ◽  
F. C. Jain ◽  
J. E. Ayers
Keyword(s):  
Thermal Annealing ◽  
Annealing Temperature ◽  
Complete Removal ◽  
Threading Dislocation ◽  
Threading Dislocations ◽  
Material System ◽  
Novel Approach ◽  
Dislocation Densities ◽  
Microscopic Evaluation ◽  
Heteroepitaxial Layers

ABSTRACTThe application of mismatched combinations of heteroepitaxial semiconductors has been quite limited due to the presence of high threading dislocation densities. In recent years, great progress has been made toward solving this problem using compliant substrates and lateral epitaxial overgrowth. We have proposed another approach which we call patterned heteroepitaxial processing (PHP), and which involves post-growth patterning and thermal annealing. In this paper we describe the successful application of the PHP technique to the ZnSe/GaAs (001) material system.Epitaxial layers of ZnSe on GaAs (001) were grown to thicknesses of 2000 - 6000 Å by photoassisted metalorganic vapor phase epitaxy (MOVPE). Following growth, layers were patterned by photolithography and then annealed at elevated temperature under flowing hydrogen. Threading dislocation densities were determined using a bromine/methanol etch followed by microscopic evaluation of the resulting etch pit densities.We found that as-grown layers contained more than 107 cm-2 threading dislocations. The complete removal of threading dislocations was accomplished by patterning to 70 μm by 70 μm square regions followed by thermal annealing for 30 minutes at temperatures greater than 500°C. Neither post-growth annealing alone nor post-growth patterning alone had a significant effect. By studying the annealing temperature dependence, we have determined that the dislocation removal by PHP is thermally activated. It appears that the maximum dimension for patterned regions in PHP is determined by the annealing temperature rather than an effective range for image forces.These results show that PHP can be used to completely remove threading dislocations from lattice-relaxed heteroepitaxial layers. In principle this approach should be generally applicable to mismatched heteroepitaxial materials.

Control of threading dislocations in lattice-mismatched heteroepitaxy

1992 ◽  
Vol 263 ◽  
Author(s):  
L.J. Schowalter ◽  
A.P. Taylor ◽  
J. Petruzzello ◽  
J. Gaines ◽  
D. Olego
Keyword(s):  
Misfit Dislocation ◽  
Gaas Substrate ◽  
Strain Relaxation ◽  
Threading Dislocations ◽  
Practical Applications ◽  
Gaas Substrates ◽  
Mismatched Heteroepitaxy ◽  
Matched Layers ◽  
Heteroepitaxial Layers ◽  
Lattice Matched

ABSTRACTIt is generally observed that strain relaxation, which occurs by misfit dislocation formation, in lattice-mismatched heteroepitaxial layers is accompanied by the formation of threading dislocations. However, our group and others have observed that strain-relaxed epitaxial layers of In1−xGaxAs on GaAs substrates can be grown without the formation of threading dislocations in the epitaxial layer. We have been able to grow strain-relaxed layers up to 13% In concentration without observable densities of threading dislocations in the epilayer but do observe a large number of dislocations pushed into the GaAs substrate. The ability to grow strain-relaxed, lattice-mismatched heteroepitaxial layers has important practical applications. We have succeeded in growing dislocation-free layers of ZnSe on appropriately lattice-matched layers of In1−xGaxAs.

Substrate Engineering With Plastic Buffer Layers

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 45-49 ◽  
Author(s):  
Leo J. Schowalter
Keyword(s):  
Epitaxial Layer ◽  
Misfit Dislocation ◽  
Lattice Mismatch ◽  
Lattice Parameter ◽  
Buffer Layers ◽  
Threading Dislocation ◽  
Threading Dislocations ◽  
Substrate Engineering ◽  
Two Sides ◽  
Heteroepitaxial Layers

The advantage that epitaxy offers the electronics and optoelectronics industries is that it allows the possibility of producing precisely controlled layers of very high crystal quality. Heteroepitaxy of different materials offers the promise of tailoring device layers in clever ways that nature did not intend. However unlike fruit juices, nature has made it difficult to epitaxially combine different materials. As the preceding articles have clearly pointed out, it is very difficult to obtain smooth epitaxial layers that are free both of defects and strain when there is a lattice mismatch between the layers and their substrates.As already discussed in this issue, a uniform network of dislocations at the interface between a flat, uniform epitaxial layer and its substrate can completely relieve strain in the majority of the epitaxial layer. This would be a satisfactory situation for many devices so long as the active region of the device could be kept away from the interface. The problem is how to introduce the dislocations in an appropriate way. When an epitaxial layer has a larger lattice parameter than the underlying substrate, a misfit dislocation running along the interface represents a plane of atoms that has been removed from the epitaxial layer. (One would insert a plane of atoms if the epitaxial lattice parameter was smaller. For simplicity however we will continue to assume that the epitaxial layer has a larger lattice parameter.) It is not possible for a whole half plane of atoms, bounded by the dislocation at the interface and the substrate edges along the two sides, to be removed at once. The boundary between where the extra plane of atoms has been removed and where the epitaxial layer has not relaxed yet will represent a threading dislocation. This threading dislocation would continue to move as the size of the misfit dislocation along the interface grows. Ideally it moves all the way out to the substrate edge and vanishes there while the misfit dislocation along the interface would end up extending from one side of the substrate to the other. However other dislocations and other kinds of defects can effectively pin the threading dislocation resulting in an epitaxial layer with many threading dislocations. Unfortunately these threading dislocations are generally detrimental to most kinds of devices. It is precisely this high density of threading dislocations that limits applications of many heteroepitaxial layers.

Anisotropy of interfacial defects in the initial stage of MOVPE GaAs growth On Si

1990 ◽  
Vol 48 (4) ◽  
pp. 592-593
Author(s):  
C. Vannuffel ◽  
C. Schiller ◽  
J. P. Chevalier
Keyword(s):  
Early Stage ◽  
Threading Dislocations ◽  
Mbe Growth ◽  
Detailed Mechanism ◽  
Si Substrates ◽  
Initial Stage ◽  
Interfacial Defects ◽  
Interfacial Dislocations ◽  
Step Growth ◽  
Essential Problem

Recently, interest has focused on the epitaxy of GaAs on Si as a promising material for electronic applications, potentially for integration of optoelectronic devices on silicon wafers. The essential problem concerns the 4% misfit between the two materials, and this must be accommodated by a network of interfacial dislocations with the lowest number of threading dislocations. It is thus important to understand the detailed mechanism of the formation of this network, in order to eventually reduce the dislocation density at the top of the layers.MOVPE growth is carried out on slightly misoriented, (3.5°) from (001) towards , Si substrates. Here we report on the effect of this misorientation on the interfacial defects, at a very early stage of growth. Only the first stage, of the well-known two step growth process, is thus considered. Previously, we showed that full substrate coverage occured for GaAs thicknesses of 5 nm in contrast to MBE growth, where substantially greater thicknesses are required.

ВЛИЯНИЕ ТВЕРДОФАЗНОЙ РЕКРИСТАЛЛИЗАЦИИ С ДВОЙНОЙ ИМПЛАНТАЦИЕЙ НА ПЛОТНОСТЬ СТРУКТУРНЫХ ДЕФЕКТОВ В УЛЬТРАТОНКИХ СЛОЯХ КРЕМНИЯ НА САПФИРЕ

2020 ◽  
Vol 96 (3s) ◽  
pp. 154-159
Author(s):  
Н.Н. Егоров ◽  
С.А. Голубков ◽  
С.Д. Федотов ◽  
В.Н. Стаценко ◽  
А.А. Романов ◽  
...  
Keyword(s):  
Dislocation Density ◽  
Solid Phase ◽  
Modern Method ◽  
Structural Defects ◽  
Structural Quality ◽  
Mos Transistors ◽  
Ultrathin Layers ◽  
Heteroepitaxial Layers ◽  
Xrd And Tem

Высокая плотность структурных дефектов является основной проблемой при изготовлении электроники на гетероструктурах «кремний на сапфире» (КНС). Современный метод получения ультратонких структур КНС с помощью твердофазной эпитаксиальной рекристаллизации позволяет значительно снизить дефектность в гетероэпитаксиальном слое КНС. В данной работе ультратонкие (100 нм) слои КНС были получены путем рекристаллизации и утонения субмикронных (300 нм) слоев кремния на сапфире, обладающих различным структурным качеством. Плотность структурных дефектов в слоях КНС оценивалась с помощью рентгеноструктурного анализа и просвечивающей электронной микроскопии. Кривые качания от дифракционного отражения Si(400), полученные в ω-геометрии, продемонстрировали максимальную ширину на полувысоте пика не более 0,19-0,20° для ультратонких слоев КНС толщиной 100 нм. Формирование структурно совершенного субмикронного слоя КНС 300 нм на этапе газофазной эпитаксии обеспечивает существенное уменьшение плотности дислокаций в ультратонком кремнии на сапфире до значений ~1 • 104 см-1. Тестовые n-канальные МОП-транзисторы на ультратонких структурах КНС характеризовались подвижностью носителей в канале 725 см2 Вс-1. The high density of structural defects is the main problem on the way to the production of electronics on silicon-on-sapphire (SOS) heteroepitaxial wafers. The modern method of obtaining ultrathin SOS wafers is solid-phase epitaxial recrystallization which can significantly reduce the density of defects in the SOS heteroepitaxial layers. In the current work, ultrathin (100 nm) SOS layers were obtained by recrystallization and thinning of submicron (300 nm) SOS layers, which have various structural quality. The density of structural defects in the layers was estimated by using XRD and TEM. Full width at half maximum of rocking curves (ω-geometry) was no more than 0.19-0.20° for 100 nm ultra-thin SOS layers. The structural quality of 300 nm submicron SOS layers, which were obtained by CVD, depends on dislocation density in 100 nm ultrathin layers. The dislocation density in ultrathin SOS layers was reduced by ~1 • 104 cm-1 due to the utilization of the submicron SOS with good crystal quality. Test n-channel MOS transistors based on ultra-thin SOS wafers were characterized by electron mobility in the channel 725 cm2 V-1 s-1.

Local current leakage at threading dislocations in GaN bulk single crystals grown by a modified Na-flux method

2019 ◽  
Vol 58 (5) ◽  
pp. 050918 ◽  
Author(s):  
Takeaki Hamachi ◽  
Tetsuya Tohei ◽  
Masayuki Imanishi ◽  
Yusuke Mori ◽  
Akira Sakai
Keyword(s):  
Single Crystals ◽  
Threading Dislocations ◽  
Flux Method ◽  
Current Leakage ◽  
Local Current ◽  
Bulk Single Crystals

Misfit and threading dislocations in HgCdTe epitaxy

1986 ◽  
Vol 4 (4) ◽  
pp. 2200-2204 ◽  
Author(s):  
Andrei Szilagyi ◽  
Michael N. Grimbergen
Keyword(s):  
Threading Dislocations
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