scholarly journals Testing the effect of galactic feedback on the IGM atz∼ 6 with metal-line absorbers

2016 ◽  
Vol 461 (1) ◽  
pp. 606-626 ◽  
Author(s):  
Laura C. Keating ◽  
Ewald Puchwein ◽  
Martin G. Haehnelt ◽  
Simeon Bird ◽  
James S. Bolton
Keyword(s):  
Metal Line ◽  
Galactic Feedback

scholarly journals z ~ 6 metal-line absorbers as a probe of galactic feedback models

2016 ◽  
Vol 11 (S321) ◽  
pp. 75-77
Author(s):  
Laura C. Keating ◽  
Ewald Puchwein ◽  
Martin G. Haehnelt ◽  
Simeon Bird ◽  
James S. Bolton
Keyword(s):  
Incidence Rate ◽  
Equivalent Width ◽  
Intergalactic Medium ◽  
Ionization State ◽  
Metal Line ◽  
Galactic Wind ◽  
Metal Absorption ◽  
Width Distribution ◽  
The Mean ◽  
Galactic Feedback

AbstractObservations of metal absorption lines in the spectra of QSOs out to z > 6 are providing an important probe into the enrichment and ionization state of the intergalactic medium (IGM) at the tail end of reionization. Using simulations with four different feedback models, including the Illustris and Sherwood simulations, we investigate how the overall incidence rate and equivalent width distribution of metal-line absorbers varies with the galactic wind scheme. The low-ionization absorbers are reasonably insensitive to the feedback implementation, with all models reasonably close to the observed incidence rate of O i absorbers. However, all of our models struggle to reproduce the observations of C iv, which is probing overdensities close to the mean at z ~ 6, suggesting that the metals are not being transported out into the IGM efficiently enough in these simulations.

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

A Latent Issue of Via Resistance: Mechanism and Solution

2018 ◽  
Author(s):  
Wentao Qin ◽  
Scott Donaldson ◽  
Dan Rogers ◽  
Lahcen Boukhanfra ◽  
Julien Thiefain ◽  
...  
Keyword(s):  
Thermal Stress ◽  
Chemical Mechanical Planarization ◽  
Resistance Mechanism ◽  
Formation Enthalpy ◽  
Metal Line ◽  
Device Failure ◽  
Valence Electrons ◽  
Wafer Processing ◽  
Field Failure ◽  
And Tungsten

Abstract Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.

Automatic Determination of Optimal FIB Operations for Improved Circuit Probing and Fast Reconfiguration

2000 ◽  
Author(s):  
Romain Desplats ◽  
Timothee Dargnies ◽  
Jean-Christophe Courrege ◽  
Philippe Perdu ◽  
Jean-Louis Noullet
Keyword(s):  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Devices ◽  
Front Side ◽  
Automatic Determination ◽  
Metal Line ◽  
New Approach ◽  
Metal Layers

Abstract Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.

Latch-Up Induced Slit Voiding in Aluminum Metal Lines

1999 ◽  
Author(s):  
Chunyu Zhang ◽  
Lakshmi Vedula ◽  
Shekhar Khandekar
Keyword(s):  
High Temperature ◽  
Line Width ◽  
Fold Increase ◽  
Metal Line ◽  
Operating Life ◽  
Mixed Signal ◽  
Aluminum Metal ◽  
Temperature Operating ◽  
Latch Up

Abstract Latch-up induced during High Temperature Operating Life (HTOL) test of a mixed signal device fabricated with 1.0 μm CMOS, double poly, double metal process caused failures due to an open in aluminum metal line. Metal lines revealed wedge voids of about 50% of the line width. Triggering of latch up mechanism during the HTOL test resulted in a several fold increase of current flowing through the ground metal line. This increase in current resulted in the growth of the wedge voids leading to failures due to open metal lines.

Quantitative Electrical Analysis of FIB Prepared Vias on BiCMOS and CMOS090 Designs

2006 ◽  
Author(s):  
B. Domengès ◽  
P. Poirier
Keyword(s):  
Ion Beam ◽  
Beam Current ◽  
Kelvin Probe ◽  
Metal Line ◽  
Cross Sectional ◽  
Probe Technique ◽  
Cross Sectional Analysis ◽  
Controlling Parameter ◽  
Electrical Analysis ◽  
Sectional Analysis

Abstract In this study, the resistance of FIB prepared vias was characterized by the Kelvin probe technique and their physical characteristics studied using cross-sectional analysis. Two domains of resistivity were isolated in relation to the ion beam current used for the deposition of the via metal (Pt). Also submicrometer vias were investigated on 4.2 µm deep metal lines of a BiCMOS aluminum based design and a CMOS 090 copper based one. It is shown that the controlling parameter is the shape and volume of the contact, and that the contact formation is favored by the amount of over-mill of the via into the metal line it will contact.

scholarly journals GaInP/GaAs/poly-Si Multi-Junction Solar Cells by in Metal Balls Bonding

Crystals ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 726
Author(s):  
Ray-Hua Horng ◽  
Yu-Cheng Kao ◽  
Apoorva Sood ◽  
Po-Liang Liu ◽  
Wei-Cheng Wang ◽  
...  
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
Low Temperature ◽  
Triple Junction ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Open Circuit ◽  
Metal Line ◽  
Solar Simulator ◽  
Junction Solar Cell

In this study, a mechanical stacking technique has been used to bond together the GaInP/GaAs and poly-silicon (Si) solar wafers. A GaInP/GaAs/poly-Si triple-junction solar cell has mechanically stacked using a low-temperature bonding process which involves micro metal In balls on a metal line using a high-optical-transmission spin-coated glue material. Current–voltage measurements of the GaInP/GaAs/poly-Si triple-junction solar cells have carried out at room temperature both in the dark and under 1 sun with 100 mW/cm2 power density using a solar simulator. The GaInP/GaAs/poly-Si triple-junction solar cell has reached an efficiency of 24.5% with an open-circuit voltage of 2.68 V, a short-circuit current density of 12.39 mA/cm2, and a fill-factor of 73.8%. This study demonstrates a great potential for the low-temperature micro-metal-ball mechanical stacking technique to achieve high conversion efficiency for solar cells with three or more junctions.

scholarly journals The impact of galactic feedback on the circumgalactic medium

2015 ◽  
Vol 448 (1) ◽  
pp. 895-909 ◽  
Author(s):  
Joshua Suresh ◽  
Simeon Bird ◽  
Mark Vogelsberger ◽  
Shy Genel ◽  
Paul Torrey ◽  
...  
Keyword(s):  
Circumgalactic Medium ◽  
The Impact ◽  
Galactic Feedback

scholarly journals Multi frequency multi bit amplitude modulation of spoof surface plasmon polaritons by schottky diode bridged interdigital SRRs

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Haotian Ling ◽  
Baoqing Zhang ◽  
Mingming Feng ◽  
Pengfei Qian ◽  
Yiming Wang ◽  
...  
Keyword(s):  
Surface Plasmon ◽  
Surface Plasmon Polaritons ◽  
Amplitude Modulation ◽  
Schottky Diodes ◽  
Ring Resonators ◽  
Dual Frequency ◽  
Metal Line ◽  
Resonant Frequencies ◽  
Plasmon Polaritons ◽  
Spoof Surface Plasmon Polaritons

AbstractMulti-frequency multi-bit programmable amplitude modulation (AM) of spoof surface plasmon polaritons (SPPs) is realized at millimeter wave frequencies with interdigital split-ring resonators (SRRs) and In-Ga-Zn-O (IGZO) Schottky diodes. Periodic SRRs on a metal line guide both SRR mode and spoof SPP mode, the former of which rejects the spoof SPP propagation at the SRR resonant frequencies. To actively modulate the amplitude of spoof SPPs, IGZO Schottky diodes are fabricated in the SRR gaps, which continuously re-configure SRRs to metallic loops by applying bias. Interdigital gaps are designed in SRRs to increase the capacitance, thus red shifting the resonant frequencies, which significantly broadens the operation bandwidth of multi-frequency AM. Thus, cascading different kinds of interdigital SRRs with Schottky diodes enables multi-frequency multi-bit AM programmable. As a demonstration, a dual-frequency device was fabricated and characterized, which achieved significant multi-bit AM from −12.5 to −6.2 dB at 34.7 GHz and from −26 to −8.5 dB at 50 GHz independently and showed programmable capability.

Sign in / Sign up

Export Citation Format

Share Document