A Phase-Based Approach for On-Chip Bus Architecture Optimization

2008 ◽  
Vol 52 (6) ◽  
pp. 626-645 ◽  
Author(s):  
J. Lee ◽  
H.-J. Lee ◽  
C. Lee
Keyword(s):  
On Chip ◽  
Bus Architecture ◽  
Architecture Optimization

Serial-Link Bus: A Low-Power On-Chip Bus Architecture

2009 ◽  
Vol 56 (9) ◽  
pp. 2020-2032 ◽  
Author(s):  
M. Ghoneima ◽  
Y. Ismail ◽  
M.M. Khellah ◽  
J. Tschanz ◽  
V. De
Keyword(s):  
Low Power ◽  
Serial Link ◽  
On Chip ◽  
Bus Architecture

scholarly journals Design of AMBA AXI4 protocol for System-on-Chip communication

2012 ◽  
pp. 38-42
Author(s):  
Shaila S Math ◽  
Manjula R B
Keyword(s):  
System On Chip ◽  
Hardware Description Language ◽  
Test Cases ◽  
Description Language ◽  
Write Response ◽  
Hardware Description ◽  
Simulation Results ◽  
On Chip ◽  
Ip Blocks ◽  
Bus Architecture

Advanced microcontroller bus architecture (AMBA) protocol family provides metric-driven verification of protocol compliance, enabling comprehensive testing of interface intellectual property (IP) blocks and system-on-chip (SoC) designs. The AMBA advanced extensible interface 4 (AXI4) update to AMBA AXI3 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI4 also includes information on the interoperability of components. AMBA AXI4 protocol system supports 16 masters and 16 slaves interfacing. This paper presents a work aimed to design the AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are shown in Verilog compiler simulator (VCS) tool. The operating frequency is set to 100MHz. Two test cases are run to perform multiple read and multiple write operations. To perform single read operation module takes 160ns and for single write operation it takes 565ns.

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