Low-thermal-budget (300 °C) ferroelectric TiN/Hf0.5Zr0.5O2/TiN capacitors realized using high-pressure annealing

2021 ◽  
Vol 119 (24) ◽  
pp. 242901
Author(s):  
Si Joon Kim ◽  
Yong Chan Jung ◽  
Jaidah Mohan ◽  
Hyo Jeong Kim ◽  
Sung Min Rho ◽  
...  
Keyword(s):  
High Pressure ◽  
Thermal Budget ◽  
Low Thermal Budget

Formation of High Quality Oxynitride Gate Dielectrics by High Pressure Thermal Oxidation of Si in NO

1999 ◽  
Vol 567 ◽  
Author(s):  
S. C. Song ◽  
C. H. Lee ◽  
H. F. Luan ◽  
D. L. Kwong ◽  
M. Gardner ◽  
...  
Keyword(s):  
High Pressure ◽  
Gate Dielectrics ◽  
Nitrogen Concentration ◽  
Budget Process ◽  
High Nitrogen ◽  
High Quality ◽  
Thermal Budget ◽  
Hot Carrier ◽  
Low Thermal Budget ◽  
High Nitrogen Concentration

ABSTRACTIn this paper, we report a novel low thermal budget process (<800°C) for engineered ultra thin oxynitride dielectrics with high nitrogen concentration (>5% a.c.) using vertical high pressure (VHP) process. VHP grown oxynitride films show >1 OX lower leakage current, higher drive current and superior hot-carrier reliability compared to control SiO2 of identical thickness (Tox,eq) grown by RTP in O2.

Low Thermal Budget Monolithic Integration of Evanescent-Coupled Ge-on-SOI Photodetector on Si CMOS Platform

2010 ◽  
Vol 16 (1) ◽  
pp. 106-113 ◽  
Author(s):  
Kah-Wee Ang ◽  
Tsung-Yang Liow ◽  
Ming-Bin Yu ◽  
Qing Fang ◽  
Junfeng Song ◽  
...  
Keyword(s):  
Monolithic Integration ◽  
Thermal Budget ◽  
Low Thermal Budget

Improved PBTI reliability in junction-less nFET fabricated at low thermal budget for 3D Sequential Integration

2018 ◽  
Author(s):  
Zhicheng Wu ◽  
Jacopo Franco ◽  
Anne Vandooren ◽  
Ben Kaczer ◽  
Philippe Roussel ◽  
...  
Keyword(s):  
Thermal Budget ◽  
Low Thermal Budget

Low Thermal Budget Crystallization of Amorphous Silicon by Nanoclusters

2009 ◽  
Vol 12 (9) ◽  
pp. H319 ◽  
Author(s):  
Il-Suk Kang ◽  
Sung-Hun Yu ◽  
Hyun-Sang Seo ◽  
Jeong-Hun Kim ◽  
Jun-Mo Yang ◽  
...  
Keyword(s):  
Amorphous Silicon ◽  
Thermal Budget ◽  
Low Thermal Budget

Implementation of Wafer Level Packaging KOZ using SU-8 as Dielectric for the Merging of WL Fan Out to Microfluidic and Biomedical Applications

2017 ◽  
Vol 2017 (1) ◽  
pp. 000569-000575 ◽  
Author(s):  
André Cardoso ◽  
Raquel Pinto ◽  
Elisabete Fernandes ◽  
Steffen Kroehnert
Keyword(s):  
Biomedical Applications ◽  
Microfluidic Channel ◽  
Cost Effective ◽  
Curing Temperature ◽  
Microfluidic Channels ◽  
Wafer Level ◽  
Thermal Budget ◽  
Chip Area ◽  
Wide Range ◽  
Low Thermal Budget

Abstract Due to its versatility for high density, heterogeneous integration, Wafer Level Fan Out (WLFO) packaging has recently seen a tremendous growth in a broad array of applications, from telecommunications and automotive, to optical and environmental sensing, while addressing the challenges of the next big wave of the Internet of Things (IoT). In this context, WLFO is continuously being challenged to include new families of MEMS/NEMS/MOEMS sensors, low thermal budget devices and biochips with microfluidics for biomedical applications. Recent developments in WLFO technology by NANIUM [1] demonstrated the implementation of a keep-out-zone (KOZ) mechanism intended to 1st) protect sensitive sensor areas during the backend processing of WLFO wafers and 2nd) create open zones on the Re-Distribution Layers (RDL). This way, the KOZ mechanism provides a physical, direct path from the embedded device to the environment. This is a necessary feature for environment sensing (e.g., pressure) or to create optical paths free of dielectric and protected from the harsh chemistry steps of the WLFO process. This paper describes new developments on KOZ, implemented with SU-8 photoresist as a WLFO dielectric, whose application is a novelty in the WLFO platform. The use of SU-8 and the KOZ with it, addresses some gaps of the current WLFO technology towards the integration of chips with bio-sensitive areas and sensors with low thermal budget. Due to its well-known bio-compatibility and inert behavior, SU-8 can be used as a neutral dielectric to be in direct contact to target fluids (e.g., sera, blood). Also, due to its low curing temperature, SU-8 allows a very low temperature WLFO process and thus the embedding of temperature-limited devices that have been outside the WLFO realm, for example, magneto-resistive or magnetic-spin sensor chips, which degrades its performance above 160°C. More interestingly, SU-8 exhibits a particular non-conformal behavior, which creates very smooth surfaces even over the mildly rough mold compound area of a fan-out package. Adding to this, SU-8 is readily available in the market in a wide range of thicknesses, spanning from 0.5 μm to &gt;100 μm, and further allowing multiple spin coatings to build thick layers. Thus, SU-8 can provide smooth and deep enough channels for microfluidic flow over the chip sensing areas and, at the same time, provide the necessary layer thickness discrimination for the KOZ mechanism. Combining these features, the SU-8 layers in WLFO can play the triple role of 1) RDL dielectric insulation, 2) KOZ mechanism and 3) embedded microfluidic channels as part of the RDL. In summary, besides the unprecedented use of SU-8 in WLFO packaging, KOZ implementation on SU-8 provides a true, attainable bridge between WLFO and integrated microfluidic applications, for biosensing and biomedical applications in general. Outlooking the potentialities of such a merge, a Fan-Out package can embed several chips interconnected by RDL lines, as it currently allows, and also connected by microfluidic channel for multi-point, multi-function biosensing, constituting a true Lab-on-Package, cost-effective solution. Instead of building all sensing areas and microfluidic channels over a large silicon (Si) chip, this solution builds the feed-in, feed-out areas of the microfluidic channel over the inexpensive fan-out area, minimizing the sensing chip area, with the consequent front-end cost reduction.

Sign in / Sign up

Export Citation Format

Share Document