Performance improvement of DVB-T2 SFNS by using MISO transmission scheme

periodically in preparing learning plans, implementing learning, assessing learning achievement, carrying out follow-up assessments of student learning achievement that can improve teacher performance. This performance improvement is through periodic collaborative educational supervision. Based on the results of educational supervision in cycle I and cycle II, teacher performance increased, namely in cycle I, teacher performance in preparing learning plans in cycle I reached 71.98%, while cycle II was 92.44%. Teacher performance in implementing learning cycle I reached 72.44% while cycle II reached 93.81%. Teacher performance in assessing learning achievement in cycle Im reached 81.30% while cycle II was 90.56%. Teacher performance in carrying out follow-up assessments of student learning achievement in the first cycle reached 59.76% while the second cycle was 83.00%. Thus, the average action cycle II was above 75.00%. Based on the results of this study, it can be concluded that the teacher's performance has increased in preparing learning plans, implementing learning, assessing learning achievement, carrying out follow-up assessments of student learning achievement.

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Business Performance Improvement Perception Using Business process Re-engineering (BPR): The case of Kosova SMEs

10.33107/ubt-ic.2018.332 ◽

2018 ◽

Author(s):

Uran Mujku

Keyword(s):

Performance Improvement ◽

Business Process ◽

Business Performance

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CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

ELECTRICAL AND COMPUTER SYSTEMS ◽

10.15276/eltecs.33.109.2020.3 ◽

2020 ◽

Vol 33 (109) ◽

pp. 21-31

Author(s):

І. Ya. Zeleneva ◽

Т. V. Golub ◽

T. S. Diachuk ◽

А. Ye. Didenko

Keyword(s):

Performance Improvement ◽

Experimental Studies ◽

Production Costs ◽

Floating Point ◽

Computing Device ◽

Quartus Ii ◽

Functional Blocks ◽

Mental Testing ◽

Processor Cores ◽

Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

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