Investigation on interface charges in SiN/AlxGa1−xN/GaN heterostructures by analyzing the gate-to-channel capacitance and the drain current behaviors

2021 ◽  
Vol 130 (10) ◽  
pp. 105704
Author(s):  
Bledion Rrustemi ◽  
Marie-Anne Jaud ◽  
François Triozon ◽  
Clémentine Piotrowicz ◽  
William Vandendaele ◽  
...  
Keyword(s):  
Drain Current ◽  
Interface Charges

LOW FREQUENCY NOISE IN SUB-0.1μmSiGepMOSFETs, CHARACTERISATION AND MODELING

2004 ◽  
Vol 04 (02) ◽  
pp. L309-L318 ◽  
Author(s):  
KRUNOSLAV ROMANJEK ◽  
GÉRARD GHIBAUDO ◽  
THOMAS ERNST ◽  
JAN A. CHROBOCZEK
Keyword(s):  
Low Frequency ◽  
Hole Mobility ◽  
Drain Current ◽  
Frequency Noise ◽  
Transport Parameters ◽  
Noise Sources ◽  
Interface Charges ◽  
Power Spectral ◽  
Strong Inversion ◽  
Channel Lengths

Drain current-gate voltage, I d ( V g ) characteristics and the power spectral density, PSD , of I d fluctuations were obtained on SiGe channel pMOSFETs and on their Si homologues, for I d intensities varied from deep sub-threshold to strong inversion values. Devices with 2.2nm thick SiO 2 gates and channel lengths 50 nm <L<10μm were used. In heterostructures, the SiGe layers were 20nm thick and buried under 2nm of Si . The data were simulated, assuming a parallel current flow in the interface and the SiGe channels, with associated noise sources. The transport parameters, extracted from I d ( V g ) characteristics, served for calculating the PSD ( I d ) functions. The latter required adjusting the interface trap density and a parameter α c , accounting for the effect of the interface charge fluctua-tions on the hole mobility fluctuations, significant at high levels of trap filling i.e. high I d . We found that the PSD in the SiGe devices was up to 10 times lower than in the Si controls at sufficiently high I d . The simulation, accounting for the data, required a significant lowering of α c for the SiGe channel. That implies that the LFN reduction in SiGe MOSFETs results from a weaker interaction of the SiGe holes with the interface charges. The sub-0.1μm channel devices show a similar noise lowering, in spite of the hole mobility degradation.

ION IMPLANTED InP MISFET's WITH LOW DRAIN CURRENT DRIFT

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-223-C4-226 ◽  
Author(s):  
G. POST ◽  
P. DIMITRIOU ◽  
A. FALCOU ◽  
N. DUHAMEL ◽  
G. MERMANT
Keyword(s):  
Drain Current ◽  
Current Drift ◽  
Ion Implanted

Effect of Illumination on Organic Polymer Thin-Film Transistors

2003 ◽  
Vol 771 ◽  
Author(s):  
Michael C. Hamilton ◽  
Sandrine Martin ◽  
Jerzy Kanicki
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Drain Current ◽  
Charge Carriers ◽  
Electrical Performance ◽  
Organic Polymer ◽  
Light Illumination ◽  
Polymer Thin Film ◽  
Channel Region ◽  
White Light Illumination

AbstractWe have investigated the effects of white-light illumination on the electrical performance of organic polymer thin-film transistors (OP-TFTs). The OFF-state drain current is significantly increased, while the drain current in the strong accumulation regime is relatively unaffected. At the same time, the threshold voltage is decreased and the subthreshold slope is increased, while the field-effect mobility of the charge carriers is not affected. The observed effects are explained in terms of the photogeneration of free charge carriers in the channel region due to the absorbed photons.

High-current recessed gate enhancement-mode ultrawide bandgap Al x Ga1−x N channel MOSHFET with drain current 0.48 A mm−1 and threshold voltage +3.6 V

2021 ◽  
Vol 14 (1) ◽  
pp. 014003
Author(s):  
Shahab Mollah ◽  
Kamal Hussain ◽  
Abdullah Mamun ◽  
Mikhail Gaevski ◽  
Grigory Simin ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
High Current ◽  
Enhancement Mode ◽  
Recessed Gate

An Analytical Drain Current Model for Dual-material Gate Graded - channel and Dual-oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET

2019 ◽  
Vol 9 (2) ◽  
pp. 291-297
Author(s):  
Hind Jaafar ◽  
Abdellah Aouaj ◽  
Ahmed Bouziane ◽  
Benjamin Iñiguez
Keyword(s):  
Current Model ◽  
Drain Current ◽  
Oxide Thickness ◽  
Subthreshold Current ◽  
The Poisson Equation ◽  
Strong Inversion ◽  
Cylindrical Form ◽  
Silvaco Atlas ◽  
Dual Material ◽  
Good Agreement

Background: A novel Dual Material Gate Graded Channel and Dual Oxide Thickness Cylindrical Gate (DMG-GC-DOT) MOSFET is presented in this paper. Methods: Analytical model of drain current is developed using a quasi-two-dimensional cylindrical form of the Poisson equation and is expressed as a function of the surface potential, which is calculated using the expressions of the current density. Results: Comparison of the analytical results with 3D numerical simulations using Silvaco Atlas - TCAD software presents a good agreement from subthreshold to strong inversion regime and for different bias voltages. Conclusion: Two oxide thicknesses with different permittivity can effectively improve the subthreshold current of DMG-GC-DOT MOSFET.

Mechanism of drain current droop in GaAs MESFETs

1995 ◽  
Vol 31 (21) ◽  
pp. 1875-1876 ◽  
Author(s):  
P.H. Ladbrooke ◽  
A.K. Jastrzebski ◽  
J.P. Bridge ◽  
R.J. Donarski ◽  
J.E. Barnaby
Keyword(s):  
Drain Current

Wide range modulation of synaptic weight in thin-film transistors with hafnium oxide gate insulator and indium-zinc oxide channel layer for artificial synapse application

Nanoscale ◽  
2021 ◽  
Author(s):  
Keonwon Beom ◽  
Jimin Han ◽  
Hyun-Mi Kim ◽  
Tae-Sik Yoon
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistors ◽  
Hafnium Oxide ◽  
Synaptic Weight ◽  
Drain Current ◽  
Gate Insulator ◽  
Channel Layer ◽  
Indium Zinc Oxide ◽  
Wide Range

Wide range synaptic weight modulation with a tunable drain current was demonstrated in thin-film transistors (TFTs) with a hafnium oxide (HfO2−x) gate insulator and an indium-zinc oxide (IZO) channel layer...

scholarly journals Equivalent Circuit Modeling of a Dual-Gate Graphene FET

Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 63
Author(s):  
Saima Hasan ◽  
Abbas Z. Kouzani ◽  
M A Parvez Mahmud
Keyword(s):  
Equivalent Circuit ◽  
Gate Voltage ◽  
Voltage Dependence ◽  
Drain Current ◽  
Bilayer Graphene ◽  
Circuit Modeling ◽  
Equivalent Circuit Modeling ◽  
Dual Gate ◽  
Source Voltage ◽  
Transit Frequency

This paper presents a simple and comprehensive model of a dual-gate graphene field effect transistor (FET). The quantum capacitance and surface potential dependence on the top-gate-to-source voltage were studied for monolayer and bilayer graphene channel by using equivalent circuit modeling. Additionally, the closed-form analytical equations for the drain current and drain-to-source voltage dependence on the drain current were investigated. The distribution of drain current with voltages in three regions (triode, unipolar saturation, and ambipolar) was plotted. The modeling results exhibited better output characteristics, transfer function, and transconductance behavior for GFET compared to FETs. The transconductance estimation as a function of gate voltage for different drain-to-source voltages depicted a proportional relationship; however, with the increase of gate voltage this value tended to decline. In the case of transit frequency response, a decrease in channel length resulted in an increase in transit frequency. The threshold voltage dependence on back-gate-source voltage for different dielectrics demonstrated an inverse relationship between the two. The analytical expressions and their implementation through graphical representation for a bilayer graphene channel will be extended to a multilayer channel in the future to improve the device performance.

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