Direct confirmation of structural differences in single Shockley stacking faults expanding from different origins in 4H-SiC PiN diodes

2020 ◽  
Vol 128 (8) ◽  
pp. 085705 ◽  
Author(s):  
J. Nishio ◽  
A. Okada ◽  
C. Ota ◽  
R. Iijima
Keyword(s):  
Stacking Faults ◽  
Pin Diodes ◽  
Structural Differences ◽  
Different Origins ◽  
Direct Confirmation

Effect of Stacking Faults Originating from Half Loop Arrays on Electrical Behavior of 10 kV 4H-SiC PiN Diodes

2012 ◽  
Vol 717-720 ◽  
pp. 387-390 ◽  
Author(s):  
Robert E. Stahlbush ◽  
Qing Chun Jon Zhang ◽  
Anant K. Agarwal ◽  
Nadeemullah A. Mahadik
Keyword(s):  
Basal Plane ◽  
Forward Bias ◽  
Stacking Faults ◽  
Device Fabrication ◽  
Electrical Behavior ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Electrical Stress ◽  
Half Loop

The effects of Shockley stacking faults (SSFs) that originate from half loop arrays (HLAs) on the forward voltage and reverse leakage were measured in 10 kV 4H-SiC PiN diodes. The presence of HLAs and basal plane dislocations in each diode in a wafer was determined by ultraviolet photoluminescence imaging of the wafer before device fabrication. The SSFs were expanded by electrical stressing under forward bias of 30 A/cm2, and contracted by annealing at 550 °C. The electrical stress increased both the forward voltage and reverse leakage. Annealing returned the forward voltage and reverse leakage to nearly their original behavior. The details of SSF expansion and contraction from a HLA and the effects on the electrical behavior of the PiN diodes are discussed.

Temperature dependence of forward I -V in SiC pin diodes considering stacking faults

2013 ◽  
Vol 10 (11) ◽  
pp. 1409-1412 ◽  
Author(s):  
K. Ohtsuka ◽  
A. Furukawa ◽  
R. Tanaka ◽  
S. Yamamoto ◽  
S. Nakata
Keyword(s):  
Temperature Dependence ◽  
Stacking Faults ◽  
Pin Diodes

Mechanisms of Stacking Fault Growth in SiC PiN Diodes

2004 ◽  
Vol 815 ◽  
Author(s):  
R. E. Stahlbush ◽  
M. E. Twigg ◽  
J. J. Sumakeris ◽  
K. G. Irvine ◽  
P. A. Losee
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Stacking Fault ◽  
Drift Region ◽  
Pin Diodes ◽  
Current Time ◽  
Partial Dislocations ◽  
Initial Evolution ◽  
A Chain ◽  
Fault Growth

AbstractThe early development of stacking faults in SiC PiN diodes fabricated on 8° off c-axis 4H wafers has been studied. The 150μm drift region and p-n junction were epitaxially grown. The initial evolution of the stacking faults was examined by low injection electroluminescence using current-time product steps as low as 0.05 coul/cm2. The properties of the dislocations present before electrical stressing were determined based on previously observed differences of Si-core and C-core partial dislocations and the patterns of stacking fault expansion. The initial stacking fault expansion often forms a chain of equilateral triangles and at higher currents and/or longer times these triangles coalesce. All of the faulting examined in this paper originated between 10 and 40 μm below the SiC surface. The expansion rate of the bounding partial dislocations is very sensitive to the partials' line directions, their core types and the density of kinks. From these patterns it is concluded that the stacking faults originate from edge-like basal plane dislocations that have Burgers vectors either parallel or anti-parallel to the off-cut direction. Evidence for dislocation conversions between basal-plane and threading throughout the epitaxial drift region is also presented.

Injected carrier concentration dependence of the expansion of single Shockley-type stacking faults in 4H-SiC PiN diodes

2018 ◽  
Vol 123 (2) ◽  
pp. 025707 ◽  
Author(s):  
T. Tawara ◽  
S. Matsunaga ◽  
T. Fujimoto ◽  
M. Ryo ◽  
M. Miyazato ◽  
...  
Keyword(s):  
Carrier Concentration ◽  
Concentration Dependence ◽  
Stacking Faults ◽  
Pin Diodes

Study of Forward Voltage Drift in Diffused SiC PiN Diodes Doped by Al or B

2005 ◽  
Vol 483-485 ◽  
pp. 989-992 ◽  
Author(s):  
S.I. Maximenko ◽  
Stanislav I. Soloviev ◽  
A.E. Grekov ◽  
A.V. Bolotnikov ◽  
Ying Gao ◽  
...  
Keyword(s):  
Current Density ◽  
Room Temperature ◽  
Stacking Faults ◽  
Applied Current ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Applied Current Density ◽  
Voltage Drift ◽  
Significant Change ◽  
Degradation Testing

The degradation of diffused SiC PIN diodes during forward-biased operation was studied by first fabricating PIN diodes by diffusion of aluminum or boron into 4H-SiC substrates with n-type 10-15 µm thick epilayers doped by nitrogen up to 5x1015cm-3. The formed diodes were subjected to degradation testing under an applied current density of 200A/cm2 at room temperature. The majority of the Al diffused diodes demonstrated a voltage drift, ΔVf, of more than 2 V, while B-doped diodes showed no significant change in forward voltage. The EBIC mode of SEM was employed to monitor nucleation and expansion of stacking faults.

Overlapping Shockley/Frank Faults in 4H-SiC PiN Diodes

2006 ◽  
Vol 527-529 ◽  
pp. 383-386 ◽  
Author(s):  
Mark E. Twigg ◽  
Robert E. Stahlbush ◽  
Peter A. Losee ◽  
Can Hua Li ◽  
I. Bhat ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Light Emission ◽  
Stacking Faults ◽  
Dark Field ◽  
Pin Diodes ◽  
Plan View ◽  
Planar Defects ◽  
Burgers Vector ◽  
Partial Dislocations ◽  
Transmission Electron

Using light emission imaging (LEI), we have determined that not all planar defects in 4H-SiC PiN diodes expand in response to bias. Accordingly, plan-view transmission electron microscopy (TEM) observations of these diodes indicate that these static planar defects are different in structure from the mobile stacking faults (SFs) that have been previously observed in 4H-SiC PiN diodes. Bright and dark field TEM observations reveal that such planar defects are bounded by partial dislocations, and that the SFs associated with these partials display both Frank and Shockley character. That is, the Burgers vector of such partial dislocations is 1/12<4-403>. For sessile Frank partial dislocations, glide is severely constrained by the need to inject either atoms or vacancies into the expanding faulted layer. Furthermore, these overlapping SFs are seen to be fundamentally different from other planar defects found in 4H-SiC.

Partial Dislocations and Stacking Faults in 4H-SiC PiN Diodes

2004 ◽  
Vol 457-460 ◽  
pp. 537-542 ◽  
Author(s):  
Mark E. Twigg ◽  
Robert E. Stahlbush ◽  
M. Fatemi ◽  
Steve Arthur ◽  
Jeffery B. Fedison ◽  
...  
Keyword(s):  
Stacking Faults ◽  
Pin Diodes ◽  
Partial Dislocations

Performance of Silicon Carbide PiN Diodes Fabricated on Basal Plane Dislocation-Free Epilayers

2006 ◽  
Vol 527-529 ◽  
pp. 371-374 ◽  
Author(s):  
Ze Hong Zhang ◽  
A.E. Grekov ◽  
Priyamvada Sadagopan ◽  
S.I. Maximenko ◽  
Tangali S. Sudarshan
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Surface Damage ◽  
Induced Current ◽  
Pin Diodes ◽  
Current Stressing ◽  
Forward Current ◽  
Nucleation Sites ◽  
Basal Plane Dislocation ◽  
Electron Beam Induced Current

The nucleation sites of stacking faults (SFs) during forward current stress operation of 4H-SiC PiN diodes were investigated by the electron beam induced current (EBIC) mode of scanning electron microscopy (SEM), and the primary SF nucleation sites were found to be basal plane dislocations (BPDs). Damage created on the diode surface also acts as SF nucleation sites. By using a novel BPD-free SiC epilayer, and avoiding surface damage, PiN diodes were fabricated which did not exhibit SF formation under current stressing at 200A/cm2 for 3 hours.

VF Degradation of 4H-SiC PiN Diodes Using Low-BPD Wafers

2014 ◽  
Vol 778-780 ◽  
pp. 851-854 ◽  
Author(s):  
Chiharu Ota ◽  
Johji Nishio ◽  
Kazuto Takao ◽  
Takashi Shinohe
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Optical Observation ◽  
Etch Pits ◽  
Pin Diodes ◽  
Bipolar Devices ◽  
Basal Plane Dislocation ◽  
Pl Mapping ◽  
Koh Etching ◽  
Free Area

In this paper, we found origin of VFdegradation of SiC bipolar devices other than a basal plane dislocation (BPD) in the SiC substrate. A VFdegradation of the 4H-SiC PiN diodes with low-BPD wafers was evaluated and its origins were discussed. Some diodes suffered VFdegradation, even though they were fabricated on BPD-free area. PL mapping, TEM image, and optical observation after KOH etching showed that there were Shockley stacking faults and combined etch-pits arrays, which were presumed to be caused by the device process.

3.3 kV-10A 4H-SiC PiN Diodes

2008 ◽  
Vol 600-603 ◽  
pp. 991-994 ◽  
Author(s):  
Pierre Brosselard ◽  
Nicolas Camara ◽  
Jawad ul Hassan ◽  
Xavier Jordá ◽  
Peder Bergman ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
Leakage Current ◽  
Substrate Surface ◽  
Stacking Faults ◽  
Pin Diodes ◽  
Reverse Mode ◽  
Low Leakage ◽  
Innovative Process ◽  
Low Leakage Current ◽  
Bipolar Conduction

An innovative process has been developed by Linköping University to prepare the 4HSiC substrate surface before epitaxial growth. The processed PiN diodes have been characterized in forward and reverse mode at different temperature. The larger diodes (2.56 mm2) have a very low leakage current around 20 nA @ 500V for temperatures up to 300°C. A performant yield (68%) was obtained on these larger diodes have a breakdown voltage superior to 500V. Electroluminescence characteristics have been done on these devices and they show that there is no generation of Stacking Faults during the bipolar conduction.

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