Low-temperature p-type ohmic contact to WSe2 using p+-MoS2/WSe2 van der Waals interface

2020 ◽  
Vol 117 (15) ◽  
pp. 153101
Author(s):  
Kei Takeyama ◽  
Rai Moriya ◽  
Kenji Watanabe ◽  
Satoru Masubuchi ◽  
Takashi Taniguchi ◽  
...  
Nano Letters ◽  
2017 ◽  
Vol 17 (8) ◽  
pp. 4781-4786 ◽  
Author(s):  
Xu Cui ◽  
En-Min Shih ◽  
Luis A. Jauregui ◽  
Sang Hoon Chae ◽  
Young Duck Kim ◽  
...  

2018 ◽  
Vol 924 ◽  
pp. 389-392 ◽  
Author(s):  
Mattias Ekström ◽  
Shuoben Hou ◽  
Hossein Elahipanah ◽  
Arash Salemi ◽  
Mikael Östling ◽  
...  

Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.


2017 ◽  
Vol 56 (4S) ◽  
pp. 04CR15 ◽  
Author(s):  
Haruka Shimizu ◽  
Akio Shima ◽  
Yasuhiro Shimamoto ◽  
Noriyuki Iwamuro

Author(s):  
K. Kakushima ◽  
Y. Ikeuchi ◽  
T. Hoshii ◽  
I. Muneta ◽  
H. Wakabayashi ◽  
...  
Keyword(s):  

2002 ◽  
Vol 46 (5) ◽  
pp. 689-693 ◽  
Author(s):  
S.E. Mohney ◽  
B.A. Hull ◽  
J.Y. Lin ◽  
J. Crofton

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.


Materials ◽  
2021 ◽  
Vol 14 (7) ◽  
pp. 1649
Author(s):  
Gemechis D. Degaga ◽  
Sumandeep Kaur ◽  
Ravindra Pandey ◽  
John A. Jaszczak

Vertically stacked, layered van der Waals (vdW) heterostructures offer the possibility to design materials, within a range of chemistries and structures, to possess tailored properties. Inspired by the naturally occurring mineral merelaniite, this paper studies a vdW heterostructure composed of a MoS2 monolayer and a PbS bilayer, using density functional theory. A commensurate 2D heterostructure film and the corresponding 3D periodic bulk structure are compared. The results find such a heterostructure to be stable and possess p-type semiconducting characteristics. Due to the heterostructure’s weak interlayer bonding, its carrier mobility is essentially governed by the constituent layers; the hole mobility is governed by the PbS bilayer, whereas the electron mobility is governed by the MoS2 monolayer. Furthermore, we estimate the hole mobility to be relatively high (~106 cm2V−1s−1), which can be useful for ultra-fast devices at the nanoscale.


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