scholarly journals Lithography-free fabrication of low operating voltage and large channel length graphene transistor with current saturation by utilizing Li+ of ion-conducting-oxide gate dielectric

AIP Advances ◽  
2020 ◽  
Vol 10 (8) ◽  
pp. 085313
Author(s):  
Nitesh K. Chourasia ◽  
Vijay K. Singh ◽  
Anand Sharma ◽  
Anchal Srivastava ◽  
Bhola N. Pal
Keyword(s):  
Gate Dielectric ◽  
Channel Length ◽  
Operating Voltage ◽  
Current Saturation ◽  
Large Channel ◽  
Ion Conducting

Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar R. Mohapatra ◽  
Madhav P. Desai ◽  
Siva G. Narendra ◽  
V. Ramgopal Rao
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Channel Length ◽  
Mos Transistors ◽  
Short Channel ◽  
Technology Scaling ◽  
Mos Transistor ◽  
Wide Range ◽  
Impact Of Technology ◽  
The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

Metal Oxide Thin Film Transistor with Nano Inorganic Gate Dielectric : Material Chemistry, Nanoscience, Solution Processing and Electronics

2021 ◽  
Vol 23 (09) ◽  
pp. 1078-1085
Author(s):  
A. Kanni Raj ◽  
Keyword(s):  
Thin Film ◽  
Metal Oxide ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Thin Film Transistor ◽  
Sol Gel ◽  
Oxide Thin Film ◽  
Barium Zirconate ◽  
Operating Voltage ◽  
Metal Oxide Thin Film

Indium Lead Oxide (ILO) based Metal Oxide Thin Film Transistor (MOTFT) is fabricated with Lead Barium Zirconate (PBZ) gate dielectric. PBZ is formed over doped silicon substrate by cheap sol-gel process. Thin film PBZ is analysed with X-ray Diffraction (XRD), Ultra-Violet Visible Spectra (UV-Vis) and Atomic Force Microscope (AFM). IZO is used as bottom gate to contact Thin Film Transistor (TFT). This device needs only 5V as operating voltage, and so is good for lower electronics <40V. It shows excellent emobility 4.5cm2/V/s, with on/off ratio 5×105 and sub-threshold swing 0.35V/decade.

scholarly journals Theory and computational study of electrophoretic ion separation and focusing in microfluidic channels

2012 ◽  
Vol 17 (4) ◽  
pp. 431-447 ◽  
Author(s):  
Oleksiy V. Klymenko ◽  
Christian Amatore ◽  
Wen Sun ◽  
Yong-Liang Zhou ◽  
Zhao-Wu Tian ◽  
...  
Keyword(s):  
Computational Study ◽  
Electrical Contact ◽  
Channel Length ◽  
Microfluidic Channels ◽  
Solution Flow ◽  
Ion Separation ◽  
Microfluidic Separation ◽  
2D Simulation ◽  
Ion Focusing ◽  
Ion Conducting

In this work we describe the theory and 2D simulation of ion separation and focusing in a new concept of microfluidic separation device. The principle of the method of ion focusing is classical in the sense that it consists in opposing a hydrodynamic transport ensured by the solution flow to an electrophoretic driving force so that any ionic sample results poised within the microchannel at the point where the two forces equilibrate. The originality of the concept investigated here relies on the fact that thanks to the use of an ion-conducting membrane of variable thickness in electrical contact with the channel the electrophoretic force is varied continuously all along the channel length. Similarly, changing the geometric shape of the membrane allows a facile optimization of the device separation and focusing properties.

Modeling and Designing a Device Using MuGFETs

2008 ◽  
Author(s):  
V. K. Lamba ◽  
Derick Engles ◽  
S. S. Malik
Keyword(s):  
Gate Dielectric ◽  
Silicon Film ◽  
General Rule ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Radius Of Curvature ◽  
Short Channel ◽  
Dielectric Thickness ◽  
Fin Thickness

This work describes computer simulations of various, Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) with double and triple-gate structures, as well as gate-all-around devices. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. Here short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as Drain induced barrier lowering (DIBL), sub-threshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.

Future Silicon Nanocrystal Nonvolatile Memory Technology

2001 ◽  
Vol 686 ◽  
Author(s):  
Michele L. Ostraat ◽  
Jan W. De Blauwe
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Channel Length ◽  
Charge Storage ◽  
Memory Devices ◽  
Two Stage ◽  
Nanocrystal Memory

AbstractA great deal of research interest is being invested in the fabrication and characterization of nanocrystal structures as charge storage memory devices. In these flash memory devices, it is possible to measure threshold voltage shifts due to charge storage of only a few electrons per nanocrystal at room temperature. Although a variety of methods exist to fabricate nanocrystals and to incorporate them into device layers, control over the critical nanocrystal dimensions, tunnel oxide thickness, and interparticle separation and isolation remains difficult to achieve. This control is vital to produce reliable and consistent devices over large wafer areas. To address these control issues, we have developed a novel two-stage ultra clean reactor in which the Si nanocrystals are generated as single crystal, nonagglomerated, spherical aerosol particles from silane decomposition at 950°C at concentrations exceeding 108 cm−3 at sizes below 10 nm. Using existing aerosol instrumentation, it is possible to control the particle size to approximately 10% on diameter. In the second reactor, particles are passivated with a high quality oxide layer with shell thickness controllable from 0.7 to 2.0 nm. The two-stage aerosol reactor is integrated to a 200 mm wafer deposition chamber such that controlled particle densities can be deposited thermophoretically. With nanocrystal deposits of 1013 cm−2, contamination of transition metals and other elements can be controlled to less than 1010 atoms cm−2.We have fabricated 0.2 μm channel length aerosol nanocrystal floating gate memory devices using conventional MOS ULSI processing on 200 mm wafers. The aerosol nanocrystal memory devices exhibit normal transistor characteristics with drive current 30 μA/μm, subthreshold slope 200 mV/dec, and drain induced barrier lowering 100 mV/V, typical values for thick gate dielectric high substrate doped nonvolatile memory devices. Uniform Fowler-Nordheim tunneling is used to program and erase these memory devices. Despite 5 nm tunnel oxides, threshold voltage shifts > 2 V have been achieved with microsecond program and millisecond erase times at moderate operating voltages. The aerosol devices also exhibit excellent endurance cyclability with no window closure observed after 105 cycles. Furthermore, reasonable disturb times and long nonvolatility are obtained, illustrating the inherent advantage of discrete nanocrystal charge storage. No drain disturb was detected even at drain biases of 4V, indicating that little or no charge conduction occurs in the nanocrystal layer. We have demonstrated promise for aerosol nanocrystal memory devices. However, numerous issues exist for the future of nanocrystal devices. These technology issues and challenges will be discussed as directions for future work.

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