Determination of grain boundary barrier height and interface states by a focused laser beam

1983 ◽  
Vol 42 (3) ◽  
pp. 285-287 ◽  
Author(s):  
E. Poon ◽  
E. S. Yang ◽  
H. L. Evans ◽  
W. Hwang ◽  
R. M. Osgood
Keyword(s):  
Grain Boundary ◽  
Laser Beam ◽  
Barrier Height ◽  
Interface States ◽  
Grain Boundary Barrier

Solid-phase crystallization of ultra-thin amorphous Ge layers on insulators

2021 ◽  
Author(s):  
Ryo Oishi ◽  
Koji ASAKA ◽  
Bolotov Leonid ◽  
Noriyuki Uchida ◽  
Masashi Kurosawa ◽  
...  
Keyword(s):  
Grain Size ◽  
Grain Boundary ◽  
Barrier Height ◽  
Carrier Mobility ◽  
Solid Phase ◽  
Hole Mobility ◽  
Solid Phase Crystallization ◽  
Simple Method ◽  
20 Nm ◽  
Grain Boundary Barrier

Abstract A simple method to form ultra-thin (< 20 nm) semiconductor layers with a higher mobility on a 3D-structured insulating surface is required for next-generation nanoelectronics. We have investigated the solid-phase crystallization of amorphous Ge layers with thicknesses of 10−80 nm on insulators of SiO2 and Si3N4. We found that decreasing the Ge thickness reduces the grain size and increases the grain boundary barrier height, causing the carrier mobility degradation. We examined two methods, known effective to enhance the grain size in the thicker Ge (>100 nm). As a result, a relatively high Hall hole mobility (59 cm2/Vs) has been achieved with a 20-nm-thick polycrystalline Ge layer on Si3N4, which is the highest value among the previously reported works.

scholarly journals An extended grain boundary barrier height model including the impact of internal electric field

AIP Advances ◽  
2018 ◽  
Vol 8 (11) ◽  
pp. 115126 ◽  
Author(s):  
Bai-Xiang Xu ◽  
Zi-Qi Zhou ◽  
Peter Keil ◽  
Till Frömling
Keyword(s):  
Grain Boundary ◽  
Electric Field ◽  
Barrier Height ◽  
Internal Electric Field ◽  
The Impact ◽  
Height Model ◽  
Grain Boundary Barrier

Comparative Studies of Furnace and Rapid Thermal Passivation for Accumulation and Inversion Mode Polysilicon-On-Oxide Mosfets.

1990 ◽  
Vol 182 ◽  
Author(s):  
S. Batra ◽  
K. Park ◽  
S. Banerjee ◽  
R. Sundaresan
Keyword(s):  
Grain Boundary ◽  
Barrier Height ◽  
Atomic Hydrogen ◽  
Carrier Transport ◽  
Inversion Mode ◽  
Accumulation Mode ◽  
Potential Barriers ◽  
And Inversion ◽  
Channel Region ◽  
Grain Boundary Barrier

AbstractCarrier transport in the channel region of polysilicon thin film MOSFETs is affected by the presence of grain boundary potential barriers and is further complicated by the modulation of the grain boundary barrier height with gate voltage. Passivation of the trap sites with atomic hydrogen reduces the barrier height and thereby improves the performance of polysilicon transistors. In this paper, we demonstrate the effectiveness of Rapid Thermal Annealing (RTA) using Si3N4 as a solid source of H as a passivation technique for both inversion and accumulation mode polysilicon MOSFETs. ON/OFF ratios of 107 can be obtained by RTA passivation for inversion mode polysilicon MOSFETs compared to 106 after furnace passivation permitting the potential application of these MOSFETs both as load transistors in SRAMs as well as pass transistors in DRAMs. In contrast, the ON&OFF ratio of accumulation mode polysilicon MOSFETs does not show any improvement even though ID and VT improve with passivation. This is because of excessive back channel leakage in accumulation mode MOSFETs which increases with passivation.

Grain boundary barrier height in base and space charge regions

1983 ◽  
Vol 26 (11) ◽  
pp. 1069-1075 ◽  
Author(s):  
J. Dugas ◽  
J.P. Crest ◽  
C.M. Singal ◽  
J. Oualid
Keyword(s):  
Grain Boundary ◽  
Space Charge ◽  
Barrier Height ◽  
Grain Boundary Barrier
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