scholarly journals Optical properties of thin semiconductor device structures with reflective back-surface layers

1999 ◽  
Author(s):  
M. B. Clevenger ◽  
C. S. Murray ◽  
S. A. Ringel ◽  
R. N. Sacks ◽  
L. Qin ◽  
...  
Keyword(s):  
Optical Properties ◽  
Semiconductor Device ◽  
Back Surface ◽  
Surface Layers ◽  
Device Structures ◽  
Thin Semiconductor

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

TEM Sample Preparation by Single-Sided Low-Energy Ion Beam Etching

2011 ◽  
Author(s):  
Liew Kaeng Nan ◽  
Lee Meng Lung
Keyword(s):  
Sample Preparation ◽  
Semiconductor Device ◽  
Ion Beam ◽  
Critical Dimension ◽  
Low Energy ◽  
Ex Situ ◽  
Good Image Quality ◽  
Ion Beam Etching ◽  
Device Structures ◽  
Common Technique

Abstract Conventional FIB ex-situ lift-out is the most common technique for TEM sample preparation. However, the scaling of semiconductor device structures poses great challenge to the method since the critical dimension of device becomes smaller than normal TEM sample thickness. In this paper, a technique combining 30 keV FIB milling and 3 keV ion beam etching is introduced to prepare the TEM specimen. It can be used by existing FIBs that are not equipped with low-energy ion beam. By this method, the overlapping pattern can be eliminated while maintaining good image quality.

Non-Destructive Measurements of III-V Semiconductor Device Structure by a Hard X-ray Microprobe

1991 ◽  
Vol 240 ◽  
Author(s):  
F. Uchida ◽  
J. Shigeta ◽  
Y. SUZUKI
Keyword(s):  
Semiconductor Device ◽  
Film Structure ◽  
Device Structure ◽  
X Ray ◽  
Model Sample ◽  
Device Structures ◽  
The Difference ◽  
X Ray Absorption ◽  
Non Destructive ◽  
Non Destructive Characterization

ABSTRACTA non-destructive characterization technique featuring a hard X-ray Microprobe is demonstrated for lll-V semiconductor device structures. A GaAs FET with a 2 μm gate length is measured as a model sample of a thin film structure. X-ray scanning microscopic images of the FET are obtained by diffracted X-ray and fluorescence X-ray detection. Diffracted X-ray detection measures the difference in gate material and source or drain material as a gray level difference on the image due to the X-ray absorption ratio. Ni Ka fluorescence detection, on the other hand, provides imaging of 500 Å thick Ni layers, which are contained only in the source and drain metals, through non-destructive observation.

Quantitative electron holographic tomography for the 3D characterisation of semiconductor device structures

2008 ◽  
Vol 108 (11) ◽  
pp. 1401-1407 ◽  
Author(s):  
Alison C. Twitchett-Harrison ◽  
Timothy J.V. Yates ◽  
Rafal E. Dunin-Borkowski ◽  
Paul A. Midgley
Keyword(s):  
Semiconductor Device ◽  
Device Structures

Mapping of Process-Induced Dopant Redistributions by Electron Holography

2004 ◽  
Vol 10 (4) ◽  
pp. 462-469 ◽  
Author(s):  
Wolf-Dieter Rau ◽  
Alexander Orchowski
Keyword(s):  
Semiconductor Device ◽  
Device Fabrication ◽  
Electron Holography ◽  
Dopant Diffusion ◽  
Fundamental Parameters ◽  
Device Processing ◽  
Device Structures ◽  
Before And After ◽  
Potential Applications ◽  
Junction Potential

We present and review dopant mapping examples in semiconductor device structures by electron holography and outline their potential applications for experimental investigation of two-dimensional (2D) dopant diffusion on the nanometer scale. We address the technical challenges of the method when applied to transistor structures with respect to quantification of the results in terms of the 2Dp–njunction potential and critically review experimental boundary conditions, accuracy, and potential pitfalls. By obtaining maps of the inner electrostatic potential before and after anneals typically used in device processing, we demonstrate how the “vertical” and “lateral” redistribution of boron during device fabrication can directly be revealed. Such data can be compared with the results of process simulation to extract the fundamental parameters for dopant diffusion in complex device structures.

scholarly journals Adsorption and Recovery using Vaporization of Liquid Fluorocarbon Precursor

2020 ◽  
Vol 58 (6) ◽  
pp. 397-402
Author(s):  
Junyoung Park ◽  
Byoungmoon Oh ◽  
Kyongnam Kim
Keyword(s):  
Semiconductor Device ◽  
High Capacity ◽  
Etching Process ◽  
Temperature Plasma ◽  
Ion Energy ◽  
Ion Energy Distribution ◽  
Recovery Processes ◽  
Layer Structures ◽  
Device Structures ◽  
Long Time

PFC gas is primarily used during the etching process in the manufacture of ULSIs and in cleaning after CVD processes. PFC is classified as a greenhouse gas that stays in the atmosphere for a long time and has a high GWP. High capacity and high integration have been achieved in recent years as semiconductor device structures have been replaced by vertical layer structures, and the consumption of PFC gas has exploded due to the increase in high aspect ratio and patterning processes. Therefore, many researchers have been working on methods to decompose, recover, and reuse the gas after the etching process to reduce the emissions of PFC gas. In this study, etching and recovery processes were performed using C5F8 in L-FC which is in liquid phase at room temperature. Among the L-FCs, C5F8 gas has a high C/F ratio, similar to that of the C4F8 gas, which is a conventional PFC gas. In addition, to confirm its reusability, the recovered C5F8 was injected back into the chamber, and the electron temperature, plasma density, and ion energy distribution were analyzed. Based on these experimental data, the reliability of the etch processes performed with recovered C5F8 gas was evaluated, and the possibility of reusing the recovered C5F8 gas was confirmed.

Mosaic Crystal Model for Dynamical X-Ray Diffraction from Step-Graded InxGa1-xAs and InxAl1-xAs/GaAs (001) Metamorphic Buffers and Device Structures

2017 ◽  
Vol 26 (03) ◽  
pp. 1740019
Author(s):  
P. B. Rago ◽  
J. E. Ayers
Keyword(s):  
Semiconductor Device ◽  
High Electron Mobility Transistors ◽  
High Electron ◽  
X Ray Diffraction ◽  
General Applicability ◽  
X Ray ◽  
Device Structures ◽  
Mosaic Crystal ◽  
Crystal Model ◽  
Metamorphic Buffers

In this paper we apply a mosaic crystal model for dynamical x-ray diffraction to step-graded metamorphic semiconductor device structures containing dislocations. This model represents an extension of the previously-reported phase-invariant model, which is broadly applicable and serves as the basis for the x-ray characterization of metamorphic structures, allowing determination of the depth profiles of strain, composition, and dislocation density. The new model has more general applicability and is more appropriate for step-graded metamorphic device structures, which are of particular interest for high electron mobility transistors and light emitting diodes. Here we present the computational details of the mosaic crystal model and demonstrate its application to step-graded InxGa1-xAs/GaAs (001) and InxAl1-xAs/GaAs (001) metamorphic buffers and device structures.

Metrology of semiconductor device structures by cross-sectional AFM

2001 ◽  
Vol 80 (1-3) ◽  
pp. 138-141 ◽  
Author(s):  
C. Jenkins ◽  
D.I. Westwood ◽  
M. Elliott ◽  
J.E. Macdonald ◽  
C. Meaton ◽  
...  
Keyword(s):  
Semiconductor Device ◽  
Cross Sectional ◽  
Device Structures
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