Finite element simulations on piezoelectric modulation of ZnO grain boundary barrier height

2019 ◽  
Vol 126 (20) ◽  
pp. 205101 ◽  
Author(s):  
Zi-Qi Zhou ◽  
Kyle Taylor ◽  
Erion Gjonaj ◽  
Till Frömling ◽  
Bai-Xiang Xu
Author(s):  
Ryo Oishi ◽  
Koji ASAKA ◽  
Bolotov Leonid ◽  
Noriyuki Uchida ◽  
Masashi Kurosawa ◽  
...  

Abstract A simple method to form ultra-thin (< 20 nm) semiconductor layers with a higher mobility on a 3D-structured insulating surface is required for next-generation nanoelectronics. We have investigated the solid-phase crystallization of amorphous Ge layers with thicknesses of 10−80 nm on insulators of SiO2 and Si3N4. We found that decreasing the Ge thickness reduces the grain size and increases the grain boundary barrier height, causing the carrier mobility degradation. We examined two methods, known effective to enhance the grain size in the thicker Ge (>100 nm). As a result, a relatively high Hall hole mobility (59 cm2/Vs) has been achieved with a 20-nm-thick polycrystalline Ge layer on Si3N4, which is the highest value among the previously reported works.


AIP Advances ◽  
2018 ◽  
Vol 8 (11) ◽  
pp. 115126 ◽  
Author(s):  
Bai-Xiang Xu ◽  
Zi-Qi Zhou ◽  
Peter Keil ◽  
Till Frömling

1983 ◽  
Vol 42 (3) ◽  
pp. 285-287 ◽  
Author(s):  
E. Poon ◽  
E. S. Yang ◽  
H. L. Evans ◽  
W. Hwang ◽  
R. M. Osgood

2007 ◽  
Vol 129 (4) ◽  
pp. 513-522 ◽  
Author(s):  
Eric Loomis ◽  
Pedro Peralta ◽  
Damian C. Swift

Two methods have been used to simulate 2D elastic wave scattering in nickel aluminide (NiAl) bicrystals to study effects of grain boundaries and material anisotropy on elastic wave propagation. Scattering angles and amplitude ratios of the reflected and refracted waves produced at the grain boundary were calculated via slowness curves for both grains, which were plotted in the plane of incidence containing the grain boundary normal. From these curves, scattering angles were measured graphically and amplitude ratios were calculated based on the continuity of tractions and displacements at the boundary. To support these calculations, finite element simulations were performed with ABAQUS/EXPLICIT to obtain time- and space-dependent stresses. The results of each method correlated well with each other for four bicrystals. It was found that for bicrystals where the transmitted quasi-longitudinal (TQL) wave amplitude decreased across the boundary, diminished stresses were found in the finite element models for the same bicrystal. Conversely, where an increase in amplitude of the TQL wave was found, the finite element simulations showed that stress under the boundary increased. In general, the amplitude of the TQL wave was found to have a strong connection to the ratio of incident and TQL sound speeds. However, other directions in each grain are believed to contribute strongly to the overall scattering process since the pairs of bicrystals in this investigation had somewhat similar sound speeds. These findings correlated well with free surface cracking observed in a previous paper (Loomis, E., Peralta, P., Swift, D., and McClellan, K., 2005, Mater. Sci. Eng., Ser. A., 404(1-2), pp. 291–300), where cracks nucleated and propagated due to the focusing of scattered waves at the boundary. Specifically, in bicrystals oriented for shielding, the grain boundary was protected forcing cracks to grow outside of the shielded region.


1990 ◽  
Vol 182 ◽  
Author(s):  
S. Batra ◽  
K. Park ◽  
S. Banerjee ◽  
R. Sundaresan

AbstractCarrier transport in the channel region of polysilicon thin film MOSFETs is affected by the presence of grain boundary potential barriers and is further complicated by the modulation of the grain boundary barrier height with gate voltage. Passivation of the trap sites with atomic hydrogen reduces the barrier height and thereby improves the performance of polysilicon transistors. In this paper, we demonstrate the effectiveness of Rapid Thermal Annealing (RTA) using Si3N4 as a solid source of H as a passivation technique for both inversion and accumulation mode polysilicon MOSFETs. ON/OFF ratios of 107 can be obtained by RTA passivation for inversion mode polysilicon MOSFETs compared to 106 after furnace passivation permitting the potential application of these MOSFETs both as load transistors in SRAMs as well as pass transistors in DRAMs. In contrast, the ON&OFF ratio of accumulation mode polysilicon MOSFETs does not show any improvement even though ID and VT improve with passivation. This is because of excessive back channel leakage in accumulation mode MOSFETs which increases with passivation.


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