Researchers model high-speed drop impact on thin films

Scilight ◽  
2017 ◽  
Vol 2017 (8) ◽  
pp. 080005
Author(s):  
Meeri Kim
Keyword(s):  
2021 ◽  
Vol 6 (4) ◽  
Author(s):  
Samya Sen ◽  
Anthony G. Morales ◽  
Randy H. Ewoldt
Keyword(s):  

2009 ◽  
Vol 131 (1) ◽  
Author(s):  
J. J. M. Zaal ◽  
W. D. van Driel ◽  
F. J. H. G. Kessels ◽  
G. Q. Zhang

The increased use of mobile appliances such as mobile phones and navigation systems in today’s society has resulted in an increase in reliability issues related to drop performance. Mobile appliances are dropped several times during their lifespan and the product is required to survive common drop accidents. A widely accepted method to assess the drop reliability of microelectronics on board-level is the drop impact test. This test has been standardized by international councils such as Joint Electron Device Engineering Council and is widely adopted throughout the industry. In this research the solder loading is investigated by combining high-speed camera measurements of several drop impact tests with verified finite element models. These simulation models are developed in order to gain an insight on the loading pattern of solder joints based on interconnect layout, drop conditions, and product specifications prior to physical prototyping. Deflections and frequencies during drop testing are measured using a high-speed camera setup. The high-speed camera experiments are performed on two levels: machine level (rebounds with and without a catcher) and product level (with different levels of energy and different pulse times). Parametric (dynamic and quasistatic) 3D models are developed to predict the drop impact performance. The experimental results are used to verify and enhance the simulation models, e.g., by tuning the damping parameters. As a result, the verified models can be used to determine the location of the critical solder joint and to obtain estimates of the solder lifetime performance.


2019 ◽  
Vol 11 (50) ◽  
pp. 47153-47161 ◽  
Author(s):  
Seon Baek Lee ◽  
Boseok Kang ◽  
Daegun Kim ◽  
Chaneui Park ◽  
Seulwoo Kim ◽  
...  

2011 ◽  
Vol 1345 ◽  
Author(s):  
Yichun Zhou

ABSTRACTFerroelectric field effect transistor (FFET) is a promising candidate for non-volatile random access memory because of its high speed, single device structure, low power consumption, and nondestructive read-out operation. Currently, however, such ideal devices are commercially not available due to poor interface properties between ferroelectric film and Si substrate, such as leakage current and interdiffusion etc. So we choose YSZ and HfO2 insulating thin films as buffer layer due to they possess relatively high dielectric constant, high thermal stability, low leakage current, and good interface property with Si substrates. Two structural diodes of Pt/BNT/YSZ/Si and Pt/SBT/HfO2/Si were fabricated, and the microstructures, interface properties, C-V, I-V, and retention properties were investigated in detail. Experimental results show that the fabricated diodes exhibit excellent long-term retention properties, which is due to the good interface and the low leakage density, demonstrating that the YSZ and HfO2 buffer layers are playing a critical modulation role between the ferroelectric thin film and Si substrate.


2020 ◽  
Vol 2 (9) ◽  
pp. 4172-4178
Author(s):  
Matias Kalaswad ◽  
Bruce Zhang ◽  
Xuejing Wang ◽  
Han Wang ◽  
Xingyao Gao ◽  
...  

Integration of highly anisotropic multiferroic thin films on silicon substrates is a critical step towards low-cost devices, especially high-speed and low-power consumption memories.


2014 ◽  
Vol 93 ◽  
pp. 4-7 ◽  
Author(s):  
Yifeng Hu ◽  
Xiaoyi Feng ◽  
Jiwei Zhai ◽  
Ting Wen ◽  
Tianshu Lai ◽  
...  

2017 ◽  
Vol 38 (12) ◽  
pp. 1709-1720
Author(s):  
Shihao Yang ◽  
Yi An ◽  
Qingquan Liu
Keyword(s):  

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