scholarly journals Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel width

AIP Advances ◽  
2016 ◽  
Vol 6 (1) ◽  
pp. 015311
Author(s):  
Myunghwan Ryu ◽  
Franklin Bien ◽  
Youngmin Kim
Keyword(s):  
Logic Gate ◽  
Channel Width ◽  
Double Gate ◽  
Asymmetric Channel

scholarly journals Characteristics of gate-all-around silicon nanowire field effect transistors with asymmetric channel width and source/drain doping concentration

2012 ◽  
Vol 112 (3) ◽  
pp. 034513 ◽  
Author(s):  
Chang-Ki Baek ◽  
Sooyoung Park ◽  
Myung-Dong Ko ◽  
Taiuk Rim ◽  
Seongwook Choi ◽  
...  
Keyword(s):  
Field Effect ◽  
Doping Concentration ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Channel Width ◽  
Asymmetric Channel

scholarly journals Double-Gate Operation of Metal Nanodot-Array-Based Single-Electron Device

2022 ◽  
Author(s):  
Takayuki Gyakushi ◽  
Ikuma Amano ◽  
Atsushi Tsurumaki-Fukuchi ◽  
Masashi Arita ◽  
Yasuo Takahashi
Keyword(s):  
Coulomb Blockade ◽  
Logic Gate ◽  
Structural Complexity ◽  
Drain Current ◽  
Single Electron ◽  
Double Gate ◽  
Gate Operation ◽  
Nanodot Array ◽  
Geometrical Effect ◽  
Single Electron Device

Abstract Multidot single-electron devices (SEDs) can realize new types of computing technologies, such as reconfigurable and reservoir computing. The self-assembled metal nanodot-array film attached with multiple gates is a candidate for use in such SEDs to achieve high functionality. However, the single-electron properties of such a film have not yet been investigated in use with optimally controlled multiple gates because of structural complexity having many nanodots. In this study, Fe nanodot-array-based double-gate SEDs were fabricated and their single-electron properties modulated by the top- and bottom-gate voltages (VT and VB, respectively) were investigated. As reported in our previous study, the drain current (ID) exhibited clear oscillations against VB (i.e., Coulomb blockade oscillation) in a part of the devices, originating from a single dot among several dots. The phase of the Coulomb blockade oscillation systematically shifted with VT, indicating that the charge state of the single dot was clearly controlled by both the gate voltages despite the multidot structure and the metal multidot SED has potential for logic-gate operation. The top and bottom gates affected the electronic state of the dot unevenly owing to the geometrical effect caused by the dot shape and size of the surrounding dots.

Simulation of Segmented Double-Gate MOSFETs

2012 ◽  
Vol 721 ◽  
pp. 325-330
Author(s):  
Andras Reichardt ◽  
Gábor Varga
Keyword(s):  
Semiconductor Manufacturing ◽  
Manufacturing Technology ◽  
Channel Width ◽  
Double Gate ◽  
Double Gate Mosfet ◽  
Simulation Results

Nowdays semiconductor manufacturing technology approaches its limit of miniaturization. There is a need for devices with low impact of miniaturization on its functionality. We present here simulation results of double-gate MOSFET devices with variable silicon channel width. Effects of segmentation is shown in characteristics of devices.

Design of Universal Logic Gates Using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

2021 ◽  
Author(s):  
Lokesh B ◽  
Sai Pavan kumar K ◽  
Pown M ◽  
Lakshmi B
Keyword(s):  
Power Consumption ◽  
Logic Gate ◽  
Logic Gates ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Nand Gate ◽  
Double Gate ◽  
Nor Gate ◽  
Nor Logic Gate

Abstract This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit

Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications

2004 ◽  
Vol 48 (6) ◽  
pp. 947-959 ◽  
Author(s):  
Abhinav Kranti ◽  
Tsung Ming Chung ◽  
Denis Flandre ◽  
Jean-Pierre Raskin
Keyword(s):  
High Performance ◽  
Double Gate ◽  
Asymmetric Channel ◽  
Fully Depleted ◽  
Channel Engineering

Comparative Study on the Structural Dependence of Logic Gate Delays in Double-Gate and Triple-Gate FinFETs

2010 ◽  
Vol 10 (2) ◽  
pp. 134-142 ◽  
Author(s):  
Kwan-Young Kim ◽  
Jae-Man Jang ◽  
Dae-Youn Yun ◽  
Dong-Myong Kim ◽  
Dae-Hwan Kim
Keyword(s):  
Comparative Study ◽  
Logic Gate ◽  
Double Gate ◽  
Structural Dependence
Sign in / Sign up

Export Citation Format

Share Document