Note: A rectangular pulse generator for 50 kV voltage, 0.8 ns rise time, and 10 ns pulse width based on polymer-film switch

2015 ◽  
Vol 86 (10) ◽  
pp. 106109
Author(s):  
Hanyu Wu ◽  
Xinjun Zhang ◽  
Tieping Sun ◽  
Zhengzhong Zeng ◽  
Peitian Cong ◽  
...  
2016 ◽  
Vol 34 (4) ◽  
pp. 675-686 ◽  
Author(s):  
Z.-L. Pan ◽  
J.-H. Yang ◽  
X.-B. Cheng

AbstractAn anti-resonance pulse forming network (PFN) has been designed, analyzed, and tested for its application in generating quasi-square pulses. According to the circuit simulations, a compact generator based on two/three-section network was constructed. Two-section network is applied in the generator due to its compact structure, while three-section network is employed for generating pulses with higher quality. When two-section network is applied in the generator, the full-width at half-maximum of the load pulse is 400 ns, at the same time, its rise time, flat top and fall time are 90, 180 and 217 ns, respectively. When the three-section network is applied with the same pulse width of the load pulse, the rise time of the output decreases to 60 ns, while the flat top increases to 240 ns and the fall time reduces to 109 ns. Meanwhile, this kind of network could be used to shape the output pulses of generators whose equivalent circuit is LC series discharge network, such as MARX generator, into quasi-square pulses. And the preliminary experiment demonstrates that anti-resonance network could work well on four-stage Marx generators. A sine pulse generated by the four-stage Marx generator is shaped into a quasi-square pulse with voltage of 11.8 kV and pulse width about 110 ns based on two-section anti-resonance network.


2010 ◽  
Vol 22 (4) ◽  
pp. 787-790
Author(s):  
方进勇 Fang Jingyong ◽  
江伟华 Jiang Weihua ◽  
黄文华 Huang Wenhua

1957 ◽  
Vol 28 (7) ◽  
pp. 580-581 ◽  
Author(s):  
H. H. Wieder ◽  
D. A. Collins

1976 ◽  
Vol 14 (6) ◽  
pp. 223 ◽  
Author(s):  
B.K. Tyagi ◽  
R.K. Mehrotra

1974 ◽  
Vol 45 (12) ◽  
pp. 1546-1549 ◽  
Author(s):  
R. D. Genuario ◽  
J. C. Blackburn

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
Amit Krishna Dwivedi ◽  
Kumar Abhijeet Urma ◽  
Aminul Islam

This paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been made in terms of different parameters such as duration of incorporated delays (pulse width) and its variability with supply voltages. Further, this paper also proposes a trigger pulse generator by utilizing proposed buffered delay circuit as its basic element. Parametric results obtained for the proposed trigger pulse generator match different application specific requirements. These applications are also mentioned in this paper. The proposed trigger pulse generator requires very low supply voltage (700 mV) and also proves its effectiveness in terms of tunability of pulse width of the generated pulses. The modeling of the circuit has been done using Verilog and the simulation results are extensively verified using SPICE.


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