scholarly journals Graphene nanoribbon field-effect transistors on wafer-scale epitaxial graphene on SiC substrates

APL Materials ◽  
2015 ◽  
Vol 3 (1) ◽  
pp. 011101 ◽  
Author(s):  
Wan Sik Hwang ◽  
Pei Zhao ◽  
Kristof Tahy ◽  
Luke O. Nyakiti ◽  
Virginia D. Wheeler ◽  
...  
2016 ◽  
Vol 6 (3) ◽  
pp. 265-270 ◽  
Author(s):  
Mahdiar Ghadiry ◽  
Harith Ahmad ◽  
Chong Wu Yi ◽  
Asrulnizam Abd Manaf

2018 ◽  
Vol 86 (2) ◽  
pp. 51-57
Author(s):  
Arul Vigneswar Ravichandran ◽  
Jaebeom Lee ◽  
Lanxia Cheng ◽  
Antonio Tomas Lucero ◽  
Chadwin D Young ◽  
...  

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.


Plasmonics ◽  
2015 ◽  
Vol 11 (2) ◽  
pp. 573-577 ◽  
Author(s):  
Mahdiar Ghadiry ◽  
Harith Ahmad ◽  
Alieh Hivechi ◽  
Fatemeh Tavakoli ◽  
Asrulnizam Abd Manaf

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