scholarly journals The roles of the dielectric constant and the relative level of conduction band of high-k composite with Si in improving the memory performance of charge-trapping memory devices

AIP Advances ◽  
2014 ◽  
Vol 4 (11) ◽  
pp. 117110 ◽  
Author(s):  
Jianxin Lu ◽  
Changjie Gong ◽  
Xin Ou ◽  
Wei Lu ◽  
Jiang Yin ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Conduction Band ◽  
Memory Performance ◽  
Charge Trapping ◽  
Memory Devices ◽  
Relative Level ◽  
High K ◽  
Charge Trapping Memory

scholarly journals The effect of the thickness of tunneling layer on the memory properties of (Cu2O)0.5(Al2O3)0.5 high-k composite charge-trapping memory devices

2016 ◽  
Vol 30 (15) ◽  
pp. 1650279 ◽  
Author(s):  
Jinqiu Liu ◽  
Jianxin Lu ◽  
Jiang Yin ◽  
Bo Xu ◽  
Yidong Xia ◽  
...  
Keyword(s):  
Magnetron Sputtering ◽  
Charge Trapping ◽  
Atomic Layer ◽  
Rf Magnetron Sputtering ◽  
Memory Devices ◽  
Layer Deposition ◽  
High K ◽  
Charge Trapping Memory ◽  
Deposition Techniques ◽  
Composite Charge

The charge-trapping memory devices namely Pt/Al2O3/(Al2O[Formula: see text](Cu2O)[Formula: see text]/SiO2/[Formula: see text]-Si with 2, 3 and 4 nm SiO2 tunneling layers were fabricated by using RF magnetron sputtering and atomic layer deposition techniques. At an applied voltage of ±11 V, the memory windows in the C–V curves of the memory devices with 2, 3 and 4 nm SiO2 tunneling layers were about 4.18, 9.91 and 11.33 V, respectively. The anomaly in memory properties among the three memory devices was ascribed to the different back tunneling probabilities of trapped electrons in the charge-trapping dielectric (Al2O[Formula: see text](Cu2O)[Formula: see text] due to the different thicknesses of SiO2 tunneling layer.

Band-alignment dominated retention behaviors in high-k composite charge-trapping memory devices

2019 ◽  
Vol 114 (5) ◽  
pp. 053506 ◽  
Author(s):  
Ping Ding ◽  
Youbin Yang ◽  
Yiru Wang ◽  
Chang Liu ◽  
Jiang Yin ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Band Alignment ◽  
Memory Devices ◽  
High K ◽  
Charge Trapping Memory ◽  
Composite Charge

Enhanced charge storage performance in AlTi4Ox/Al2O3multilayer charge trapping memory devices

2014 ◽  
Vol 53 (8S3) ◽  
pp. 08NG02 ◽  
Author(s):  
Changjie Gong ◽  
Xin Ou ◽  
Bo Xu ◽  
Xuexin Lan ◽  
Yan Lei ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Charge Storage ◽  
Memory Devices ◽  
Storage Performance ◽  
Charge Trapping Memory

Novel Dual Bit Tri-Gate Charge Trapping Memory Devices

2004 ◽  
Vol 25 (12) ◽  
pp. 810-812 ◽  
Author(s):  
M. Specht ◽  
R. Kommling ◽  
F. Hofmann ◽  
V. Klandzievski ◽  
L. Dreeskornfeld ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Memory Devices ◽  
Charge Trapping Memory ◽  
Gate Charge

Effects of oxygen conditions during deposition on memory performance of metal/HfO2/SiO2/Si structured charge trapping memory

2019 ◽  
Vol 6 (8) ◽  
pp. 086306
Author(s):  
Bo Zhang ◽  
Qihang Gao ◽  
Boping Wang ◽  
Hong Wang ◽  
Chao Lu ◽  
...  
Keyword(s):  
Memory Performance ◽  
Charge Trapping ◽  
Oxygen Conditions ◽  
Charge Trapping Memory

Charge Trapping Memory Cell of TANOS (Oxide-SiN-Al2O3-TaN) Structure Erased by Fowler-Nordheim Tunneling of Holes

2006 ◽  
Vol 933 ◽  
Author(s):  
Chang-Hyun Lee ◽  
Changseok Kang ◽  
Yoocheol Shin ◽  
Jaesung Sim ◽  
Jongsun Sel ◽  
...  
Keyword(s):  
Energy Level ◽  
Threshold Voltage ◽  
Charge Trapping ◽  
Memory Cell ◽  
Floating Gate ◽  
Hole Trap ◽  
Hole Trapping ◽  
High K ◽  
Charge Trapping Memory ◽  
Nordheim Tunneling

ABSTRACTWe present the TANOS (Si-Oxide-SiN-Al2O3-TaN) cell with 40 Å-thick tunnel oxide erased by Fowler-Nordheim (FN) tunneling of hole. Thanks to introducing high-k dielectrics, alumina (Al2O3) as a blocking oxide, the erase threshold voltage can be maintained to less than - 3.0 V, meaning hole-trapping in SiN. We extracted the nitride trap densities of electron and hole for the TANOS cell. It is demonstrated that the TANOS structure is very available to investigate the trap density with shallower energy. The energy level of hole trap (1.28 eV) is found to be deeper than that of electron (0.8 eV). As the cycling stress is performed, persistent hole-trapping is observed unlike endurance characteristics of conventional floating-gate cell. The hole trapping during the cycling stress can be attributed to two possibilities. The injected holes are trapped in neutral trap of tunnel oxide and residue of holes which is not somewhat compensated by injected electrons may be accumulated in SiN. It is demonstrated the erase operation of the TANOS cell is governed by Fowler-Nordheim tunneling of hole due to the field concentration across the tunnel oxide.

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