Extremely small test cell structure for resistive random access memory element with removable bottom electrode

2014 ◽  
Vol 104 (8) ◽  
pp. 083518 ◽  
Author(s):  
Sang-Gyu Koh ◽  
Satoru Kishida ◽  
Kentaro Kinoshita
Nanoscale ◽  
2018 ◽  
Vol 10 (28) ◽  
pp. 13443-13448 ◽  
Author(s):  
Yoonho Ahn ◽  
Hyun Wook Shin ◽  
Tae Hoon Lee ◽  
Woo-Hee Kim ◽  
Jong Yeog Son

We report the effects of bottom electrode shapes on resistive random-access memory (RRAM) devices composed of Nb (bottom electrode)/NiO (dielectric)/Nb (top electrode) structures.


2020 ◽  
Vol 12 (2) ◽  
pp. 02008-1-02008-4
Author(s):  
Pramod J. Patil ◽  
◽  
Namita A. Ahir ◽  
Suhas Yadav ◽  
Chetan C. Revadekar ◽  
...  

Nanomaterials ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 1401
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko

Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.


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