Characterization of very fast states in the vicinity of the conduction band edge at the SiO2/SiC interface by low temperature conductance measurements

2014 ◽  
Vol 115 (1) ◽  
pp. 014502 ◽  
Author(s):  
Hironori Yoshioka ◽  
Takashi Nakamura ◽  
Tsunenobu Kimoto
1995 ◽  
Vol 377 ◽  
Author(s):  
G. Kawachi ◽  
M. Ishii ◽  
T. Tanaka ◽  
N. Konishi

ABSTRACTThe localized density of states (LDOS) at interfaces between intrinsic silicon and silicon nitride (Si3N4 films are studied using transient voltage spectroscopy (TVS). In the TVS technique, the transient of the voltage across a MIS-diode after a trap filling voltage pulse is measured using a high-impedance voltage probe. This allows us to make a precise measurement of the LDOS at undoped Si/insulator interfaces. The LDOS in a-Si:H/Si3N4systems has a broad peak around the energy of 0.9 eV below the conduction-band edge. A modification of the LDOS at a-Si:H/Si3N4 interfaces by bias-annealing is clearly observed using this technique. The results are consistent with the defect pool model. The LDOS in laser annealed poly-Si/Si3N4 systems has a peak centered 0.6eV below the conduction-band edge, which seems to be the Si dangling bond states in the poly-Si films.


2017 ◽  
Vol 10 (4) ◽  
pp. 046601 ◽  
Author(s):  
Tetsuo Hatakeyama ◽  
Yuji Kiuchi ◽  
Mitsuru Sometani ◽  
Shinsuke Harada ◽  
Dai Okamoto ◽  
...  

2019 ◽  
Vol 963 ◽  
pp. 175-179
Author(s):  
Judith Berens ◽  
Gregor Pobegen ◽  
Thomas Aichinger ◽  
Gerald Rescher ◽  
Tibor Grasser

We employed the thermal dielectric relaxation current method (TDRC) for the cryogenic characterization of ammonia (NH3) post oxidation annealed 4H silicon carbide (4H-SiC) trench MOSFETs. We studied differences and similarities between annealing in nitric oxide (NO) and NH3. In NO and NH3 annealed trench MOSFETs, the same type of traps was found near the conduction band edge of 4H-SiC. The TDRC-signal consists of two peaks caused by interface states with a thermal emission barrier of 0.13 eV and near interface traps (NITs) with an emission barrier of approximately 0.3 eV. Significantly more interface traps close to the conduction band edge were found for the NH3 annealed devices compared to the NO annealed ones. Our TDRC results indicate that NH3 post oxidation anneal (POA) affects trap levels in a different way than NO POA.


2008 ◽  
Vol 600-603 ◽  
pp. 755-758 ◽  
Author(s):  
Fredrik Allerstam ◽  
Einar Ö. Sveinbjörnsson

This study is focused on characterization of deep energy-level interface traps formed during sodium enhanced oxidation of n-type Si face 4H-SiC. The traps are located 0.9 eV below the SiC conduction band edge as revealed by deep level transient spectroscopy. Furthermore these traps are passivated using post-metallization anneal at 400°C in forming gas ambient.


Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 822
Author(s):  
Hyo-Jun Joo ◽  
Dae-Hwan Kim ◽  
Hyun-Seok Cha ◽  
Sang-Hun Song

We measured and analyzed the Hall offset voltages in InGaZnO thin-film transistors. The Hall offset voltages were found to decrease monotonously as the electron densities increased. We attributed the magnitude of the offset voltage to the misalignment in the longitudinal distance between the probing points and the electron density to Fermi energy of the two-dimensional electron system, which was verified by the coincidence of the Hall voltage with the perpendicular magnetic field in the tilted magnetic field. From these results, we deduced the combined conduction band edge energy profiles from the Hall offset voltages with the electron density variations for three samples with different threshold voltages. The extracted combined conduction band edge varied by a few tens of meV over a longitudinal distance of a few tenths of µm. This result is in good agreement with the value obtained from the analysis of percolation conduction.


ACS Nano ◽  
2011 ◽  
Vol 5 (7) ◽  
pp. 5888-5902 ◽  
Author(s):  
Jacek Jasieniak ◽  
Marco Califano ◽  
Scott E. Watkins

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