Advanced modeling of the effective minority carrier lifetime of passivated crystalline silicon wafers

2012 ◽  
Vol 112 (5) ◽  
pp. 054508 ◽  
Author(s):  
Fa-Jun Ma ◽  
Ganesh G. Samudra ◽  
Marius Peters ◽  
Armin G. Aberle ◽  
Florian Werner ◽  
...  
1999 ◽  
Vol 70 (10) ◽  
pp. 4044-4046 ◽  
Author(s):  
J. Gervais ◽  
O. Palais ◽  
L. Clerc ◽  
S. Martinuzzi

2013 ◽  
Vol 1536 ◽  
pp. 119-125 ◽  
Author(s):  
Guillaume Courtois ◽  
Bastien Bruneau ◽  
Igor P. Sobkowicz ◽  
Antoine Salomon ◽  
Pere Roca i Cabarrocas

ABSTRACTWe propose an implementation of the PCD technique to minority carrier effective lifetime assessment in crystalline silicon at 77K. We focus here on (n)-type, FZ, polished wafers passivated by a-Si:H deposited by PECVD at 200°C. The samples were immersed into liquid N2 contained in a beaker placed on a Sinton lifetime tester. Prior to be converted into lifetimes, data were corrected for the height shift induced by the beaker. One issue lied in obtaining the sum of carrier mobilities at 77K. From dark conductance measurements performed on the lifetime tester, we extracted an electron mobility of 1.1x104 cm².V-1.s-1 at 77K, the doping density being independently calculated in order to account for the freezing effect of dopants. This way, we could obtain lifetime curves with respect to the carrier density. Effective lifetimes obtained at 77K proved to be significantly lower than at RT and not to depend upon the doping of the a-Si:H layers. We were also able to experimentally verify the expected rise in the implied Voc, which, on symmetrically passivated wafers, went up from 0.72V at RT to 1.04V at 77K under 1 sun equivalent illumination.


2015 ◽  
Vol 242 ◽  
pp. 126-132 ◽  
Author(s):  
George Martins ◽  
Ruy S. Bonilla ◽  
Toby Burton ◽  
P. MacDonald ◽  
Peter R. Wilshaw

In this work we use Saw Damage Gettering (SDG) in combination with emitter formation to improve the minority carrier lifetime of highly contaminated multi-crystalline silicon wafers. This process is applied to wafers from the bottom of ingots, commonly referred to as the “red zone”, which are currently discarded since their high concentration of impurities limits the efficiency of solar cells produced therefrom. SDG is a potentially simple technique designed to upgrade these wafers. In this technique, bulk impurities are dissolved via annealing. The wafers are then cooled which generates a super-saturation of impurities in solution. The system then relaxes through the formation of precipitates in the saw damaged region. SDG is shown to be enhanced when using a temperature dependent cooling rate which maximizes the flux of impurities to the saw damaged regions. In addition, these benefits were observed even after an additional gettering process occurring during an emitter formation procedure. The SDG annealing conditions required to achieve the maximum lifetime were altered by the introduction of the emitter formation process. The enhancement generated by the SDG process may be sufficient to enable red-zone wafers to be processed is the same manner as higher quality no-red zone wafer wafers without adversely affecting the resultant cell efficiency. Due to its simplicity, it is expected that SDG can easily be incorporated into current production methods.


2010 ◽  
Vol 97 (9) ◽  
pp. 092109 ◽  
Author(s):  
J. A. Giesecke ◽  
M. C. Schubert ◽  
D. Walter ◽  
W. Warta

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