Electrical test method using high density plasmas for high-end printed circuit boards

2012 ◽  
Vol 83 (1) ◽  
pp. 013503
Author(s):  
Se-Jin Oh ◽  
Young-Cheol Kim ◽  
Chin-Wook Chung
2020 ◽  
Vol 17 (3) ◽  
pp. 79-88
Author(s):  
Maarten Cauwe ◽  
Bart Vandevelde ◽  
Chinmay Nawghane ◽  
Marnix Van De Slyeke ◽  
Erwin Bosman ◽  
...  

Abstract High-density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field-programmable gate arrays, digital signal processors and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of input/outputs (I/Os). To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser-drilled microvias, high-aspect ratio core vias, and small track width and spacing. Although the associated advanced manufacturing processes have been widely used in commercial, automotive, medical, and military applications, reconciling these advancements in capability with the reliability requirements for space remains a challenge. Two categories of the HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this article, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. At 1.0-mm pitch, the technology passes all testing successfully. At .8-mm pitch, failures are encountered during interconnection stress testing and conductive anodic filament testing. These failures provide the basis for updating the design rules for HDI PCBs.


Author(s):  
Jimil M. Shah ◽  
Roshan Anand ◽  
Satyam Saini ◽  
Rawhan Cyriac ◽  
Dereje Agonafer ◽  
...  

Abstract A remarkable amount of data center energy is consumed in eliminating the heat generated by the IT equipment to maintain and ensure safe operating conditions and optimum performance. The installation of Airside Economizers, while very energy efficient, bears the risk of particulate contamination in data centers, hence, deteriorating the reliability of IT equipment. When RH in data centers exceeds the deliquescent relative humidity (DRH) of salts or accumulated particulate matter, it absorbs moisture, becomes wet and subsequently leads to electrical short circuiting because of degraded surface insulation resistance between the closely spaced features on printed circuit boards. Another concern with this type of failure is the absence of evidence that hinders the process of evaluation and rectification. Therefore, it is imperative to develop a practical test method to determine the DRH value of the accumulated particulate matter found on PCBs (Printed Circuit Boards). This research is a first attempt to develop an experimental technique to measure the DRH of dust particles by logging the leakage current versus RH% (Relative Humidity percentage) for the particulate matter dispensed on an interdigitated comb coupon. To validate this methodology, the DRH of pure salts like MgCl2, NH4NO3 and NaCl is determined and their results are then compared with their published values. This methodology was therefore implemented to help lay a modus operandi of establishing the limiting value or an effective relative humidity envelope to be maintained at a real-world data center facility situated in Dallas industrial area for its continuous and reliable operation.


Sign in / Sign up

Export Citation Format

Share Document