Publisher’s Note: “Degradation of polycrystalline HfO2-based gate dielectrics under nanoscale electrical stress” [Appl. Phys. Lett. 99, 103510 (2011)]

2011 ◽  
Vol 99 (23) ◽  
pp. 239901
Author(s):  
V. Iglesias ◽  
M. Lanza ◽  
K. Zhang ◽  
A. Bayerl ◽  
M. Porti ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Stress

scholarly journals Degradation of polycrystalline HfO2-based gate dielectrics under nanoscale electrical stress

2011 ◽  
Vol 99 (10) ◽  
pp. 103510 ◽  
Author(s):  
V. Iglesias ◽  
M. Lanza ◽  
K. Zhang ◽  
A. Bayerl ◽  
M. Porti ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Stress

Gate Oxynitride Grown in N2O and Annealed in NO Using Rapid Thermal Processing

1995 ◽  
Vol 387 ◽  
Author(s):  
S. C. Sun ◽  
C. H. Chen ◽  
J. C. Lou ◽  
L. W. Yen ◽  
C. J. Lin
Keyword(s):  
Gate Dielectrics ◽  
Charge Trapping ◽  
Oxide Thickness ◽  
Interface State ◽  
No Oxidation ◽  
Nitrogen Accumulation ◽  
Electrical Stress ◽  
Wide Range ◽  
State Generation ◽  
Stress Induced Leakage Current

AbstractIn this paper a new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N2O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si-SiO2 interface than either N2O oxynitride or nitridation of SiO2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N2O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress

Effects of thermal and electrical stress on DH4T-based organic thin-film-transistors with PMMA gate dielectrics

2015 ◽  
Vol 55 (9-10) ◽  
pp. 1790-1794 ◽  
Author(s):  
N. Wrachien ◽  
N. Lago ◽  
A. Rizzo ◽  
R. D'Alpaos ◽  
A. Stefani ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gate Dielectrics ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Electrical Stress

Degradation of high-K LA2O3 gate dielectrics using progressive electrical stress

2005 ◽  
Vol 45 (9-11) ◽  
pp. 1365-1369 ◽  
Author(s):  
E. Miranda ◽  
J. Molina ◽  
Y. Kim ◽  
H. Iwai
Keyword(s):  
Gate Dielectrics ◽  
Electrical Stress ◽  
High K

Degradation Phenomena of low-temp. poly-Si TFT's Under Electrical Stress Before and After Hydrogenation

1994 ◽  
Vol 345 ◽  
Author(s):  
Y. S. Kim ◽  
K. Y. Choi ◽  
M. C. Jun ◽  
M. K. Han
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Degradation Mechanism ◽  
Charge Trapping ◽  
Gate Bias ◽  
Bias Stress ◽  
Electrical Stress ◽  
Before And After ◽  
Drain Bias ◽  
Hydrogenation Time

AbstractThe degradation mechanism in hydrogen passivated and as-fabricated poly-Si TFT's are investigated under the various electrical stress conditions. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which was stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

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