High-k (k=30) amorphous hafnium oxide films from high rate room temperature deposition

2011 ◽  
Vol 98 (25) ◽  
pp. 252903 ◽  
Author(s):  
Flora M. Li ◽  
Bernhard C. Bayer ◽  
Stephan Hofmann ◽  
James D. Dutson ◽  
Steve J. Wakeham ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Room Temperature ◽  
Oxide Films ◽  
High Rate ◽  
High K ◽  
Temperature Deposition

Room-temperature deposition of high-purity silicon oxide films by RF plasma-enhanced CVD

2001 ◽  
Vol 146-147 ◽  
pp. 451-456 ◽  
Author(s):  
Katsuya Teshima ◽  
Yasushi Inoue ◽  
Hiroyuki Sugimura ◽  
Osamu Takai
Keyword(s):  
High Purity ◽  
Room Temperature ◽  
Silicon Oxide ◽  
Oxide Films ◽  
Rf Plasma ◽  
Plasma Enhanced Cvd ◽  
High Purity Silicon ◽  
Temperature Deposition

Room Temperature Deposition of Indium Zinc Oxide Films on PES Substrate by LF Magnetron Sputtering

2007 ◽  
Vol 51 (2) ◽  
pp. 589-593 ◽  
Author(s):  
Eun Lyoung Kim ◽  
Sang Kooun Jung ◽  
Choong Soo Kim ◽  
Duck Kyu Park ◽  
Ho-Young Cho ◽  
...  
Keyword(s):  
Zinc Oxide ◽  
Magnetron Sputtering ◽  
Room Temperature ◽  
Oxide Films ◽  
Zinc Oxide Films ◽  
Indium Zinc Oxide ◽  
Temperature Deposition

Development and utility of a new 3-D magnetron source for high rate deposition of highly conductive ITO thin films near room temperature

2018 ◽  
Vol 20 (7) ◽  
pp. 4818-4830 ◽  
Author(s):  
Long Wen ◽  
Bibhuti Bhusan Sahu ◽  
Jeon Geon Han
Keyword(s):  
Thin Films ◽  
Low Temperature ◽  
Magnetron Sputtering ◽  
Room Temperature ◽  
High Rate ◽  
High Quality ◽  
Low Temperature Deposition ◽  
Ito Thin Films ◽  
Temperature Deposition ◽  
Ito Films

This study reports the high rate and low-temperature deposition of high-quality ITO films using a new 3-D confined magnetron sputtering method.

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

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