Carrier transport in polycrystalline silicon films deposited by a layer‐by‐layer technique

1994 ◽  
Vol 76 (8) ◽  
pp. 4728-4733 ◽  
Author(s):  
Deyan He ◽  
Naoto Okada ◽  
Charles M. Fortmann ◽  
Isamu Shimizu
Keyword(s):  
Polycrystalline Silicon ◽  
Carrier Transport ◽  
Silicon Films ◽  
Layer By Layer ◽  
Layer Technique ◽  
Polycrystalline Silicon Films ◽  
Layer By Layer Technique

Effect of grain alignment on lateral carrier transport in aligned-crystalline silicon films on polycrystalline substrates

2007 ◽  
Vol 22 (4) ◽  
pp. 821-825 ◽  
Author(s):  
Woong Choi ◽  
Alp T. Findikoglu ◽  
Manuel J. Romero ◽  
Mowafak Al-Jassim
Keyword(s):  
Grain Boundaries ◽  
Polycrystalline Silicon ◽  
Carrier Transport ◽  
Crystalline Silicon ◽  
Silicon Films ◽  
Dangling Bond ◽  
Grain Alignment ◽  
Bond Density ◽  
Polycrystalline Silicon Films ◽  
Trapping Sites

We report the studies on the effect of grain alignment on lateral carrier transport in nominally 〈001〉-oriented aligned-crystalline silicon (ACSi) films on polycrystalline substrates. With improving grain alignment, energy barrier height at the grain boundaries was reduced from 150 to less than 1 meV, and both conductivity and Hall mobility became less sensitive to hydrogen passivation. This suggests that the dangling bonds in ACSi films are a major source of trapping sites, and that they become less dominant with improving grain alignment. These results demonstrate that improving grain alignment enhances the lateral carrier transport in small-grained (≤1 μm) polycrystalline silicon films, by reducing dangling bond density at the grain boundaries.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Sign in / Sign up

Export Citation Format

Share Document