Conduction mechanism of high‐resistivity polycrystalline silicon films

1985 ◽  
Vol 57 (6) ◽  
pp. 2010-2013 ◽  
Author(s):  
Yoji Saito ◽  
Ichiro Mizushima ◽  
Hiroshi Kuwano
Keyword(s):  
Polycrystalline Silicon ◽  
Conduction Mechanism ◽  
Silicon Films ◽  
High Resistivity ◽  
Polycrystalline Silicon Films

Properties of furnace-annealed, high-resistivity, arsenic-implanted polycrystalline silicon films

1986 ◽  
Vol 1 (2) ◽  
pp. 311-321 ◽  
Author(s):  
W.K. Schubert
Keyword(s):  
Film Thickness ◽  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Large Fraction ◽  
Silicon Films ◽  
Grain Structure ◽  
High Resistivity ◽  
Simple Diffusion ◽  
Simple Diffusion Model ◽  
Polycrystalline Silicon Films

The approach to equilibrium of the grain structure and electrical properties has been studied in high-resistivity, As-implanted polycrystalline silicon films on thermally oxidized silicon wafers. Thermal annealing parameters are found to be critical in determining the film sheet resistance. Results from spreading resistance analysis, secondary ion mass spectroscopy, and transmission electron microscopy indicate that As diffusion down the grain boundaries into the film leads to a large fraction of the As being left in inactive grain boundary sites. Reactivation of the As is negligible when processing temperatures are 900 °C or lower. A relatively simple diffusion model has been developed that can fit the As concentration profile over the entire film thickness. This makes the model applicable to normal integrated circuit processing conditions where film thickness effects and nonequilibrium dopant distributions are important.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Structure of Annealed Polycrystalline Silicon Films. I. Recrystallization

1986 ◽  
Vol 98 (2) ◽  
pp. 383-390 ◽  
Author(s):  
F. L. Edelman ◽  
J. Heydenreich ◽  
D. Hoehl ◽  
J. Matthäi ◽  
I. Melnik ◽  
...  
Keyword(s):  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Polycrystalline Silicon Films

Stresses in thin polycrystalline silicon films

1988 ◽  
Vol 162 ◽  
pp. 365-374 ◽  
Author(s):  
V.M. Koleshko ◽  
V.F. Belitsky ◽  
I.V. Kiryushin
Keyword(s):  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Thin Polycrystalline ◽  
Polycrystalline Silicon Films
Sign in / Sign up

Export Citation Format

Share Document