scholarly journals Single-electron-based flexible multivalued logic gates

2008 ◽  
Vol 92 (9) ◽  
pp. 093101 ◽  
Author(s):  
C. K. Lee ◽  
S. J. Kim ◽  
S. J. Shin ◽  
J. B. Choi ◽  
Y. Takahashi
Keyword(s):  
Logic Gates ◽  
Single Electron ◽  
Multivalued Logic

Improvement of Single-Electron Digital Logic Gates by Utilizing Input Discretizers

2016 ◽  
Vol E99.C (2) ◽  
pp. 285-292 ◽  
Author(s):  
Tran THI THU HUONG ◽  
Hiroshi SHIMADA ◽  
Yoshinao MIZUGAKI
Keyword(s):  
Logic Gates ◽  
Single Electron ◽  
Digital Logic

scholarly journals Recent Advances on Multivalued Logic Gates: A Materials Perspective

2021 ◽  
Vol 8 (8) ◽  
pp. 2004216
Author(s):  
Sae Byeok Jo ◽  
Joohoon Kang ◽  
Jeong Ho Cho
Keyword(s):  
Logic Gates ◽  
Multivalued Logic ◽  
Recent Advances

scholarly journals Reconfigurable Logic Gates Using Single-Electron Spin Transistors

2007 ◽  
Vol 46 (10A) ◽  
pp. 6579-6585 ◽  
Author(s):  
Pham Nam Hai ◽  
Satoshi Sugahara ◽  
Masaaki Tanaka
Keyword(s):  
Electron Spin ◽  
Logic Gates ◽  
Single Electron ◽  
Reconfigurable Logic ◽  
Spin Transistors

Design of Quaternary Half Adder Using Hybrid SETMOS Cell

2011 ◽  
Vol 110-116 ◽  
pp. 5085-5089
Author(s):  
Khadijeh Feizi ◽  
Ali Shahhoseini
Keyword(s):  
Metal Oxide ◽  
Logic Gates ◽  
Metal Oxide Semiconductor ◽  
Single Electron ◽  
Oxide Semiconductor ◽  
Single Electron Transistor ◽  
Mos Transistor ◽  
Logic Operation ◽  
Half Adder ◽  
Arithmetic Units

Adder is one of the important arithmetic units in computers. In this paper, we investigate the implementation of quaternary half adder based on multiple-valued (MV) logic gates using single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. We use hybrid SETMOS universal literal gate which has been proposed by Mahapatra and Ionesco. We apply two 4-radix inputs to the proposed quaternary half adder and obtain sum and carry outputs. The logic operation of the proposed quaternary half adder is verified by using HSPICE simulator. Moreover we compare the performance of our proposed quaternary half adder with the performance of a quaternary half adder based on MOS technology.

A Novel Comparator Circuit of Single-Electron and MOS Transistors

2011 ◽  
Vol 120 ◽  
pp. 516-519
Author(s):  
You Jie Zhou ◽  
Chun Hua Xiong ◽  
Chang Bo Lu
Keyword(s):  
Logic Gates ◽  
Single Electron ◽  
Voltage Gain ◽  
Mos Transistors ◽  
Electronic Components ◽  
Single Electron Transistors ◽  
Close Analysis ◽  
Digital Comparator ◽  
Electron Transistors ◽  
Hybrid Circuit

A novel combination of single-electron transistors (SET) with MOS transistors is advanced to create inverter, which, compared with the pure SET circuit, is considerably augmented in its voltage gain and drive capability. Then a close analysis was conducted of the inverter, on the basis of which other logic gates were presented, thus achieving a circuit of two-bit digital comparator. The accuracy of the circuit is verified through the test on SPICE. This hybrid circuit shares the merits with both SET circuit and MOS circuit. Compared with the traditional circuits, this one uses fewer electronic components and is lower in power depletion.

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