Study of void formation due to electromigration in flip-chip solder joints using Kelvin bump probes

2006 ◽  
Vol 89 (3) ◽  
pp. 032103 ◽  
Author(s):  
Y. W. Chang ◽  
S. W. Liang ◽  
Chih Chen
2004 ◽  
Vol 127 (2) ◽  
pp. 120-126 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton

Understanding the formation of voids in solder joints is important for predicting the long-term reliability of solder interconnects. This paper reports experimental research on the formation of void bubbles within molten solder bumps in flip-chip connections. For flip-chip-soldered electronic components, which have small solder volume, voids can be more detrimental to reliability. A previous theory based on thermocapillary flow reveals that the direction of heating influences void formation. Using different heating profiles, 480 solder joints of flip-chip assemblies were processed. A high-lead 90Pb∕8Sn∕2Ag solder was employed in the experiments. The solder samples were microsectioned to determine the actual size or diameter of the voids. A database on sizes and locations of voids was then constructed. More defective bumps, 80%, and higher void volume were found when the solder was melted from top (flip-chip side) to bottom (test board side). The observation on cases with melting direction from bottom to top had 40% defective bumps. The results show that a single big void is near the solder bump center with a few small voids near the edge. This supports the numerical study based on the thermocapillary theory. When the melting direction was reversed, many small voids appear near the edge. Big and middle-size voids tend to stay in the middle and outer regions from top towards middle layer of the bump. This experimental finding does not completely agree with the interpretation on the formation of voids by thermocapillary theory, however, the results do show that heat flux direction plays significant role in the formation and distribution of void bubbles in molten solder.


2012 ◽  
Vol 134 (2) ◽  
Author(s):  
Subramanya Sadasiva ◽  
Ganesh Subbarayan ◽  
Lei Jiang ◽  
Daniel Pantuso

Understanding the effect of high current density on void formation and growth and relating the size of the void to the resulting electrical/mechanical failure is a critical need at the present time to ensure reliable functioning of flip-chip packages. In general, toward this end, the modeling and simulation of geometrical evolution of current induced voids have been relatively few. Simulations considering the coupled effects of mass transport through mechanisms of surface and bulk diffusion under the influence of electrical, thermal, and stress fields in solder joints leading to eventual electromigration failure do not appear to be common. In this study, we develop a phase field model for the evolution of voids under electrical, thermal, and stress fields in a flip-chip solder interconnect. We derive the equations of motion for the void accounting for energetic contributions from the active factors of surface energy, stress, and electric potential, considering both surface diffusion and transfer of the material through the bulk of the material. We describe the implementation of this model using a finite element code written in the PYTHON language, coupled with a commercial finite element solver from which we obtain the electrical, thermal, and stress fields driving the void motion. We demonstrate the implemented methodology through simulations of void evolution in flip-chip solder joints under the effects of mechanical/electrical fields and surface/bulk diffusion.


2017 ◽  
Vol 7 (1) ◽  
Author(s):  
Yuan-Wei Chang ◽  
Yin Cheng ◽  
Lukas Helfen ◽  
Feng Xu ◽  
Tian Tian ◽  
...  

2010 ◽  
Vol 2010 (1) ◽  
pp. 000234-000241
Author(s):  
Rajesh Katkar ◽  
Laura Mirkarimi

The μPILR interconnect is a copper pillar manufactured as a part of a substrate pad. In this paper, we discuss the electromigration (EM) performance of Pb-free μPILR interconnects in a multi-pair daisy chain within 150μm pitch flip-chip packages. Electromigration performance of μPILR interconnects has shown a significant improvement and noticeably delayed electromigration induced failures. Voids initially begin to appear at Cu6Sn5 and solder interface on the die side, with eventual open failure due to excessive void formation along with a severe depletion of Cu Under Bump Metallization (UBM). No failure was observed on the substrate side of the interconnect regardless of the current direction. The enhanced performance of the μPILR interconnect along with other reliability benefits makes it an excellent alternative to conventional solder joints including thin film stack UBMs, thicker copper UBM as well as copper pillar on die.


2011 ◽  
Vol 99 (8) ◽  
pp. 082114 ◽  
Author(s):  
Tian Tian ◽  
Feng Xu ◽  
Jung Kyu Han ◽  
Daechul Choi ◽  
Yin Cheng ◽  
...  

2017 ◽  
Vol 66 (4) ◽  
pp. 1229-1237 ◽  
Author(s):  
P. Wild ◽  
T. Grozinger ◽  
D. Lorenz ◽  
A. Zimmermann

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.


1998 ◽  
Vol 515 ◽  
Author(s):  
S. Wiese ◽  
F. Feustel ◽  
S. Rzepka ◽  
E. Meusel

ABSTRACTThe paper presents crack propagation experiments on real flip chip specimens applied to reversible shear loading. Two specially designed micro testers will be introduced. The first tester provides very precise measurements of the force displacement hysteresis. The achieved resolutions have been I mN for force and 20 nm for displacement. The second micro tester works similar to the first one, but is designed for in-situ experiments inside the SEM. Since it needs to be very small in size it reaches only resolutions of 10 mN and 100nm, which is sufficient to achieve equivalence to the first tester. A cyclic triangular strain wave is used as load profile for the crack propagation experiment. The experiment was done with both machines applying equivalent specimens and load. The force displacement curve was recorded using the first micro mechanical tester. From those hysteresis, the force amplitude has been determined for every cycle. All force amplitudes are plotted versus the number of cycles in order to quantify the crack length. With the second tester, images were taken at every 10th … 100th cycle in order to locate the crack propagation. Finally both results have been linked together for a combined quatitive and spatial description of the crack propagation in flip chip solder joints.


2006 ◽  
Vol 89 (22) ◽  
pp. 221906 ◽  
Author(s):  
Fan-Yi Ouyang ◽  
K. N. Tu ◽  
Yi-Shao Lai ◽  
Andriy M. Gusak

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