Pulsed plasma polymerized dichlorotetramethyldisiloxane high-k gate dielectrics for polymer field-effect transistors

2006 ◽  
Vol 99 (1) ◽  
pp. 014104 ◽  
Author(s):  
Yifan Xu ◽  
Paul R. Berger ◽  
Jai Cho ◽  
Richard B. Timmons
Keyword(s):  
Field Effect ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Pulsed Plasma ◽  
High K

scholarly journals Performance Enhancement of Electrospun IGZO-Nanofiber-Based Field-Effect Transistors with High-k Gate Dielectrics through Microwave Annealing and Postcalcination Oxygen Plasma Treatment

Nanomaterials ◽  
2020 ◽  
Vol 10 (9) ◽  
pp. 1804 ◽  
Author(s):  
Seong-Kun Cho ◽  
Won-Ju Cho
Keyword(s):  
Electrical Properties ◽  
Plasma Treatment ◽  
Field Effect ◽  
Oxygen Plasma ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Oxygen Plasma Treatment ◽  
Calcination Process ◽  
Microwave Annealing ◽  
High K

We investigated the effects of various high-k gate dielectrics as well as microwave annealing (MWA) calcination and a postcalcination oxygen plasma treatment on the electrical properties and stability of electrospun indium gallium zinc oxide (IGZO)-nanofiber (NF)-based field-effect transistors (FETs). We found that the higher the dielectric constant of the gate dielectric, the better the electric field is transferred, resulting in the better performance of the IGZO NF FET. In addition, the MWA-calcined IGZO NF FET was superior to the conventional furnace annealing-calcined device in terms of the electrical properties of the device and the operation of resistor-loaded inverter, and it was proved that the oxygen plasma treatment further improved the performance. The results of the gate bias temperature stress test confirmed that the MWA calcination process and postcalcination oxygen plasma treatment greatly improved the stability of the IGZO NF FET by reducing the number of defects and charge traps. This verified that the MWA calcination process and oxygen plasma treatment effectively remove the organic solvent and impurities that act as charge traps in the chemical analysis of NF using X-ray photoelectron spectroscopy. Furthermore, it was demonstrated through scanning electron microscopy and ultraviolet-visible spectrophotometer that the MWA calcination process and postcalcination oxygen plasma treatment also improve the morphological and optical properties of IGZO NF.

scholarly journals Simulations of the CNFETs using different high-k gate dielectrics

2020 ◽  
Vol 9 (3) ◽  
pp. 943-949
Author(s):  
Ankita Dixit ◽  
Navneet Gupta
Keyword(s):  
Carbon Nanotube ◽  
Field Effect ◽  
Gate Dielectric ◽  
Dielectric Material ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Dielectric Materials ◽  
High K ◽  
Gate Dielectric Material

In this paper we presented the analysis of Carbon Nanotube Field Effect Transistors (CNFETs) using various high-k gate dielectric materials. The objective of this work was to choose the best possible material for gate dielectric. This paper also presented the study on the effect of thickness of gate dielectric on the performance of the device. For the analysis (19, 0) CNT was considered because the diameter of (19, 0) CNT is 1.49nm and the CNFETs have been fabricated with the CNT diameter of ~1.5nm. It has been observed that La2O3 is the best gate dielectric material followed by HfO2 and ZrO2. It was also observed that as thickness of gate dielectric material reduces, drain current of CNFET increases. The outcomes of this study matches with the analytical results and hence confirm the results

Analysis of gate tunnelling currents in nanoscale metal—oxide—semiconductor field effect transistors (MOSFETs) with SiO2 and high-K gate dielectrics

2009 ◽  
Vol 223 (1) ◽  
pp. 19-24
Author(s):  
G Joshi ◽  
M Singh ◽  
M Chauhan
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Effect Of Temperature ◽  
High K ◽  
Tunnelling Current

In this paper, an analytical model for gate tunnelling current has been deployed by solving the Schrödinger equation using the Wentzel—Kramer—Brillouin approximation method for a trapezoidal potential barrier. The gate tunnelling current has been computed for direct tunnelling from channel to gate as well as for tunnelling from source drain extension region to gate. The effect of temperature variation on gate tunnelling current with an SiO2 thickness of 4nm down to 1nm has been studied at various gate voltages. Gate tunnelling in the case of high-K gate dielectrics and high-K stacks has also been analysed. In order to study the effect of temperature on gate tunnelling current in SiO2 and in high-K dielectrics, the related parameters have been modelled based on physics. The effect of variation of substrate doping concentration (Na) on gate tunnelling current in an n-type metal—oxide—semiconductor field effect transistor (n-MOSFET) with SiO2 has also been studied These studies have been used to bring out the design margins available in equivalent oxide thickness and Na.

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