Charge trapping and detrapping characteristics in hafnium silicate gate dielectric using an inversion pulse measurement technique

2005 ◽  
Vol 87 (12) ◽  
pp. 122901 ◽  
Author(s):  
Rino Choi ◽  
S. C. Song ◽  
C. D. Young ◽  
Gennadi Bersuker ◽  
Byoung Hun Lee
Keyword(s):  
Measurement Technique ◽  
Gate Dielectric ◽  
Charge Trapping ◽  
Inversion Pulse ◽  
Hafnium Silicate ◽  
Pulse Measurement

Ultrathin Gate Dielectric Growth at Reduced Pressure

1994 ◽  
Vol 342 ◽  
Author(s):  
Robert McIntosh ◽  
Carl Galewski ◽  
John Grant
Keyword(s):  
Gate Dielectric ◽  
Charge Trapping ◽  
Cmos Technology ◽  
Interface State ◽  
Constant Current ◽  
Reduced Pressure ◽  
Current Stress ◽  
Ultrathin Oxides ◽  
State Generation ◽  
Improved Characteristics

The Growth of ultrathin oxides in N2O ambient has been a subject of extensive research for submicron CMOS technology. Oxides grown in N2O tend to have a higher charge-to-breakdown, less charge trapping under constant current stress, and less interface state generation under current stress and radiation than conventional oxides grown in oxygen [1,2]. In addition the penetration of boron through N2O oxides is significantly less than through conventional thermal oxides [3]. The improved characteristics of N2O are due to an interfacial pileup of nitrogen atoms [1-3]. Thus the growth of thermal oxides in N2O provides a method for obtaining many of the more favorable aspects of reoxidized-nitrided silicon dioxides, with a much simpler process.

ZnO nanowire optoelectronic synapse for neuromorphic computing

2021 ◽  
Author(s):  
Cong Shen ◽  
Xu Gao ◽  
Cheng Chen ◽  
Shan Ren ◽  
Jianlong Xu ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Charge Trapping ◽  
Zno Nanowire ◽  
Light Pulses ◽  
Neuromorphic Hardware ◽  
Electrical Pulses ◽  
High Recognition Accuracy ◽  
A Charge ◽  
O2 Desorption

Abstract Artificial synapses that integrate functions of sensing, memory and computing are highly desired for developing brain-inspired neuromorphic hardware. In this work, an optoelectronic synapse based on the ZnO nanowire (NW) transistor is achieved, which can be used to emulate both the short-term and long-term synaptic plasticity. Synaptic potentiation is present when the device is stimulated by light pulses, arising from the light-induced O2 desorption and the persistent photoconductivity behavior of the ZnO NW. On the other hand, synaptic depression occurs when the device is stimulated by electrical pulses in dark, which is realized by introducing a charge trapping layer in the gate dielectric to trap carriers. Simulation of a neural network utilizing the ZnO NW synapses is carried out, demonstrating a high recognition accuracy over 90% after only 20 training epochs for recognizing the Modified National Institute of Standards and Technology (MNIST) digits. The present nanoscale optoelectronic synapse has great potential in the development of neuromorphic visual systems.

Charge Trapping in Hafnium Silicate Films with Modulated Composition and Enhanced Permittivity

2013 ◽  
Vol 854 ◽  
pp. 125-133 ◽  
Author(s):  
Larysa Khomenkova ◽  
Xavier Portier ◽  
Abdelilah Slaoui ◽  
Fabrice Gourbilleau
Keyword(s):  
Dielectric Constant ◽  
Electrical Properties ◽  
Magnetron Sputtering ◽  
Annealing Temperature ◽  
Annealing Treatment ◽  
Charge Trapping ◽  
Dielectric Films ◽  
Radio Frequency Magnetron Sputtering ◽  
Hafnium Silicate ◽  
Evolution Of Microstructure

Hafnium silicate dielectric films were fabricated by radio frequency magnetron sputtering. Their microstructure and electrical properties were studied versus annealing treatment. The evolution of microstructure and the formation of alternated HfO2-rich and SiO2-rich layers were observed and explained by surface directed spinodal decomposition. The stable tetragonal HfO2 phase was formed upon an annealing at 1000-1100°C. The control of annealing temperature allowed the memory window to be achieved and to be tuned as well as the dielectric constant to be enhanced.

scholarly journals Interface properties study on SiC MOS with high-k hafnium silicate gate dielectric

AIP Advances ◽  
2018 ◽  
Vol 8 (12) ◽  
pp. 125314
Author(s):  
Lin Liang ◽  
Wei Li ◽  
Sichao Li ◽  
Xuefei Li ◽  
Yanqing Wu
Keyword(s):  
Gate Dielectric ◽  
Interface Properties ◽  
Hafnium Silicate ◽  
High K

High Quality Ultrathin Gate Dielectrics Prepared by In-Situ RTP

1995 ◽  
Vol 387 ◽  
Author(s):  
L. K. Han ◽  
M. Bhat ◽  
J. Yan ◽  
D. Wristers ◽  
D. L. Kwong
Keyword(s):  
Gate Dielectric ◽  
Defect Density ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Interface State ◽  
High Quality ◽  
Hot Carrier ◽  
Thermal Oxide ◽  
State Generation

AbstractThis paper reports on the formation of high quality ultrathin oxynitride gate dielectric by in-situ rapid thermal multiprocessing. Four such gate dielectrics are discussed here; (i) in-situ NO-annealed SiO2, (ii) N2O- or NO- or O2-grown bottom oxide/RTCVD SiO2/thermal oxide, (iii) N2O-grown bottom oxide/Si3N4/N2O-oxide (ONO) and (iv) N2O-grown bottom oxide/RTCVD SiO2/N2O-oxide. Results show that capacitors with NO-based oxynitride gate dielectrics, stacked oxynitride gate dielectrics with varying quality of bottom oxide (O2/N2O/NO), and the ONO structures show high endurance to interface degradation, low defect-density and high charge-to-breakdown compared to thermal oxide. The N2O-last reoxidation step used in the stacked dielectrics and ONO structures is seen to suppress charge trapping and interface state generation under Fowler-Nordheim injection. The stacked oxynitride gate dielectrics also show excellent MOSFET performance in terms of transconductance and mobility. While the current drivability and mobilities are found to be comparable to thermal oxide for N-channel MOSFET's, the hot-carrier immunity of N-channel MOSFET's with the N2O-oxide/CVD-SiO2/N2O-oxide gate dielectrics is found to be significantly enhanced over that of conventional thermal oxide.

Sign in / Sign up

Export Citation Format

Share Document