High-temperature healing of interfacial voids in GaAs wafer bonding

2002 ◽  
Vol 91 (4) ◽  
pp. 1973-1977 ◽  
Author(s):  
YewChung Sermon Wu ◽  
Po Chun Liu ◽  
R. S. Feigelson ◽  
R. K. Route
Keyword(s):  
High Temperature ◽  
Wafer Bonding ◽  
Gaas Wafer

High performance InAs quantum dot lasers on silicon substrates by low temperature Pd-GaAs wafer bonding

2015 ◽  
Vol 107 (26) ◽  
pp. 261107 ◽  
Author(s):  
Zihao Wang ◽  
Ruizhe Yao ◽  
Stefan F. Preble ◽  
Chi-Sen Lee ◽  
Luke F. Lester ◽  
...  
Keyword(s):  
Low Temperature ◽  
Quantum Dot ◽  
Wafer Bonding ◽  
High Performance ◽  
Silicon Substrates ◽  
Quantum Dot Lasers ◽  
Gaas Wafer ◽  
Inas Quantum Dot

Introduction of high tensile strain into Ge-on-Insulator structures by oxidation and annealing at high temperature

2021 ◽  
Author(s):  
Xueyang Han ◽  
ChiaTsong Chen ◽  
Cheol-Min Lim ◽  
Kasidit Toprasertpong ◽  
Mitsuru Takenaka ◽  
...  
Keyword(s):  
Surface Roughness ◽  
High Temperature ◽  
Wafer Bonding ◽  
Present Method ◽  
Thermal Process ◽  
Tensile Strain ◽  
Process Condition ◽  
Thermal Expansion Mismatch ◽  
Physical Origin ◽  
N2 Annealing

Abstract It is demonstrated in this work that a high temperature thermal process including oxidation and N2 annealing at 850 oC can provide tensile strain of ~0.58 % at maximum into Ge-on-Insulator (GOI) structures without any special patterning or external stressors. The different impacts of oxidation and annealing on tensile strain generation, surface roughness and crystal qualities in the GOI structures fabricated by Ge condensation and wafer bonding are systematically examined. Tensile strain of 0.47 % is achieved without severe thermal damages under the optimal thermal process condition, which indicates the high potential of the present method for improving the performance of GOI n-channel MOSFETs. The influence of thermal expansion mismatch between Ge and SiO2 are suggested as a possible physical origin of high amount of tensile strain into GOI structures.

TLP Bonding Technologies for Micro Joining and 3D Packaging

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001221-001252 ◽  
Author(s):  
Kei Murayama ◽  
Mitsuhiro Aizawa ◽  
Mitsutoshi Higashi
Keyword(s):  
High Temperature ◽  
Melting Point ◽  
Low Temperature ◽  
Wafer Bonding ◽  
Bonding Process ◽  
Tlp Bonding ◽  
Hermetic Sealing ◽  
Low Temperature Bonding ◽  
Free Material ◽  
Bonding Technique

The bonding technique for High density Flip Chip(F.C.) packages requires a low temperature and a low stress process to have high reliability of the micro joining ,especially that for sensor MEMS packages requires hermetic sealing so as to ensure their performance. The Transient Liquid Phase (TLP) bonding, that is a kind of diffusion bonding is a technique that connects the low melting point material such as Indium to the higher melting point metal such as Gold by the isothermal solidification and high-melting-point intermetallic compounds are formed. Therefore, it is a unique joining technique that can achieve not only the low temperature bonding and also the high temperature reliability. The Gold-Indium TLP bonding technique can join parts at 180 degree C and after bonding the melting point of the junction is shifted to more than 495 degree C, therefore itfs possible to apply the low temperature bonding lower than the general use as a lead free material such as a SAC and raise the melting point more than AuSn solder which is used for the high temperature reliability usage. Therefore, the heat stress caused by bonding process can be expected to be lowered. We examined wafer bonding and F.C bonding plus annealing technique by using electroplated Indium and Gold as a joint material. We confirmed that the shear strength obtained at the F.C. bonding plus anneal technique was equal with that of the wafer bonding process. Moreover, it was confirmed to ensure sufficient hermetic sealing in silicon cavity packages that had been bonded at 180 degree C. And the difference of the thermal stress that affect to the device by the bonding process was confirmed. In this paper, we report on various possible application of the TLP bonding.

High-Temperature Spin-On Adhesives for Temporary Wafer Bonding

2007 ◽  
Vol 4 (3) ◽  
pp. 105-111 ◽  
Author(s):  
S. Pillalamarri ◽  
R. Puligadda ◽  
C. Brubaker ◽  
M. Wimplinger ◽  
S. Pargfrieder
Keyword(s):  
High Temperature ◽  
Wafer Bonding ◽  
Heat Dissipation ◽  
Temperature Stability ◽  
High Temperature Stability ◽  
Performance Requirements ◽  
Wide Range ◽  
Bonding Properties ◽  
Partial List ◽  
Wafer Thinning

Wafer thinning has been effectively used to improve heat dissipation in power devices and to fabricate flexible substrates, small chip packages, and multiple chips in a package. Wafer handling has become an important issue due to the tendency of thinned wafers to warp and fold. Thinned wafers need to be supported during the backgrinding process, lithography, deposition, etc. Temporary wafer bonding using removable adhesives provides a feasible route to wafer thinning. Existing adhesives meet only a partial list of performance requirements. They do not meet the requirements of high-temperature stability combined with ease of removal. This paper reports on the development of a wide range of temporary adhesives to be used in wafer thinning applications that use both novel and conventional bonding and debonding methods. We have developed a series of novel removable high-temperature spin-on adhesives with excellent bonding properties and a wide range of operating temperatures for bonding and/or debonding to achieve a better processing window.

A Bulk RF MEMS Switch by Silicon-to-GaAs Bonding

2009 ◽  
Vol 60-61 ◽  
pp. 224-227
Author(s):  
Le Lu ◽  
Jian Zhu ◽  
Shi Xin Jian ◽  
Chen Chen
Keyword(s):  
Gallium Arsenide ◽  
Transmission Line ◽  
Wafer Bonding ◽  
Gaas Substrate ◽  
Rf Mems ◽  
Beam Structure ◽  
Rf Mems Switch ◽  
Mems Switch ◽  
Gaas Wafer ◽  
Electrode Contact

. A Bulk RF MEMS switch is present in this paper. The beam structure and transmission line are separated fabricated on silicon and gallium arsenide (GaAs) wafer. The beam structure, up electrode, contact and anchor are fabricated on the silicon wafer. And transmission line and down electrode are made on the GaAs substrate. Two parts of the switch are bonded together by wafer bonding using gold layer as seed. The total area of the switch is 600 um X 600 um.

scholarly journals Interface structures in GaAs wafer bonding: Application to compliant substrates

2000 ◽  
Vol 76 (19) ◽  
pp. 2674-2676 ◽  
Author(s):  
R. R. Vanfleet ◽  
M. Shverdin ◽  
J. Silcox ◽  
Z. H. Zhu ◽  
Y. H. Lo
Keyword(s):  
Wafer Bonding ◽  
Gaas Wafer ◽  
Compliant Substrates ◽  
Interface Structures
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