Note on the thermal stresses in passivated metal interconnects

2001 ◽  
Vol 79 (11) ◽  
pp. 1706-1708 ◽  
Author(s):  
P. Sharma ◽  
H. Ardebili ◽  
J. Loman
Keyword(s):  
Thermal Stresses ◽  
Metal Interconnects ◽  
Passivated Metal

Analysis of average thermal stresses in passivated metal interconnects

1999 ◽  
Vol 86 (11) ◽  
pp. 6088-6095 ◽  
Author(s):  
A. Wikström ◽  
P. Gudmundson ◽  
S. Suresh
Keyword(s):  
Thermal Stresses ◽  
Metal Interconnects ◽  
Passivated Metal

Through Si Vias Using Liquid Metal Conductors for Re-workable 3D Electronics

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001343-001357
Author(s):  
George A. Hernandez ◽  
Daniel Martinez ◽  
Stephen Patenaude ◽  
Charles Ellis ◽  
Michael Palmer ◽  
...  
Keyword(s):  
Liquid Metal ◽  
Failure Analysis ◽  
Thermal Stresses ◽  
Electrical Contact ◽  
Additional Information ◽  
Comb Structure ◽  
Via Holes ◽  
Metal Interconnects ◽  
Electroplated Copper ◽  
Silicon Vias

This paper describes the design and fabrication of liquid metal interconnects (vias) for 2.5D and 3D integration. The liquid metal is gallium indium eutectic with a melting temperature of approximately 15.7°C that is introduced into via openings of a silicon interposer. This liquid interconnect technology can be integrated with existing interposer technologies, such as capacitors and traditional (solid metal) through-silicon vias (TSVs). In addition, liquid metal interconnects can better accommodate thermal stresses and provide re-workability in case of chip failure. Our research efforts are focused on the integration of multi-chip modules using liquid metal interconnects. Our study encompasses Direct Current (D.C.) measurements and failure analysis using snake and comb structures at low temperature (10 degrees Kelvin) to slightly above room temperature (300 degrees Kelvin). The snake and comb structure allows us to measure electrical shorts and opens, as well as provide estimates of via yield and allows additional information for determination of possible failure mechanisms. In order to make electrical contact to the liquid metal interconnect interposer from both the top and bottom, test coupons have been fabricated with arrays of large numbers of vias. The interposer structure consists of a thin (200 um thick) silicon wafer with via holes filled with liquid metal. The test coupon consists of bottom and top silicon die with a thickness of 500 um. The bottom wafer incorporates a 2 um-thick daisy-chain metallization and 100 um copper tall vias, which are electrically isolated from each other and the underlying Si by patterned AL-X dielectric. The top wafer incorporates an array of 80 um tall, electroplated copper pillars and top daisy-chain metallization. Liquid metal containment mechanisms and structures have also been investigated. In our presentation we will describe the design, fabrication and characterization of this re-workable interposer with liquid metal interconnects. We will present D.C. resistance and X-ray imagery of the liquid metal filled via. In addition, we will provide failure analysis of via yield per chip.

A Novel Technique to Re-construct 3D Void in Passivated Metal Interconnects

2003 ◽  
Vol 766 ◽  
Author(s):  
Cher Ming Tan ◽  
Zhenghao Gan ◽  
Guan Zhang ◽  
Krishnamachar Prasad ◽  
Dao Hua Zhang
Keyword(s):  
Electron Beam ◽  
Constant Current ◽  
Resistance Change ◽  
Element Simulation ◽  
Void Shape ◽  
Novel Method ◽  
Metal Interconnects ◽  
Electron Beam Heating ◽  
Transmission Information ◽  
Passivated Metal

AbstractIn the present work, a novel method is proposed to re-construct voids in passivated metal interconnections. In this method, the conventional SEM and EBIC systems are assembled and utilized without much modification. In principle, a constant current is applied to the metal interconnections while an electron beam is scanning and impinging upon the surface of the sample. The voltage at the terminals is monitored simultaneously during electron beam scanning. Resistance change, and hence voltage perturbation are expected when the electron beam approaches the defective area, caused by uneven electron beam heating (EBH) and heat transmission. Information on defects or voids is thus obtained by analyzing the voltage alteration. Finite element simulation showed that the recorded voltage perturbation is not dependent of the length of the interconnect, but a linear function of the void volume. Thus, the method is essentially useful as the metal length has increased tremendously in copper technology. In addition, it can provide the void size and depth, with the possibility to reconstruct the entire void shape in 3D.

Deformation at interfaces of Ti-6Al-4V/SiC fiber composites

1992 ◽  
Vol 50 (1) ◽  
pp. 158-159
Author(s):  
Warren J. Moberly ◽  
Daniel B. Miracle ◽  
S. Krishnamurthy
Keyword(s):  
Thermal Stresses ◽  
Load Transfer ◽  
Coefficient Of Thermal Expansion ◽  
Hot Isostatic Pressing ◽  
Matrix Composites ◽  
Ongoing Research ◽  
Aerospace Applications ◽  
Sic Fiber ◽  
The Matrix ◽  
Intermetallic Matrix Composites

Titanium-aluminum alloy metal matrix composites (MMC) and Ti-Al intermetallic matrix composites (IMC), reinforced with continuous SCS6 SiC fibers are leading candidates for high temperature aerospace applications such as the National Aerospace Plane (NASP). The nature of deformation at fiber / matrix interfaces is characterized in this ongoing research. One major concern is the mismatch in coefficient of thermal expansion (CTE) between the Ti-based matrix and the SiC fiber. This can lead to thermal stresses upon cooling down from the temperature incurred during hot isostatic pressing (HIP), which are sufficient to cause yielding in the matrix, and/or lead to fatigue from the thermal cycling that will be incurred during application, A second concern is the load transfer, from fiber to matrix, that is required if/when fiber fracture occurs. In both cases the stresses in the matrix are most severe at the interlace.

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