Shallow p-type SiGeC layers synthesized by ion implantation of Ge, C, and B in Si

1999 ◽  
Vol 75 (11) ◽  
pp. 1568-1570 ◽  
Author(s):  
H. Kurata ◽  
K. Suzuki ◽  
T. Futatsugi ◽  
N. Yokoyama
Keyword(s):  
Ion Implantation ◽  
P Type

Switching the electrical characteristics of TiO2 from n-type to p-type by ion implantation

2021 ◽  
pp. 150274
Author(s):  
Adriano Panepinto ◽  
Arnaud Krumpmann ◽  
David Cornil ◽  
Jérôme Cornil ◽  
Rony Snyders
Keyword(s):  
Ion Implantation ◽  
Electrical Characteristics ◽  
P Type

scholarly journals Detection and depth analyses of deep levels generated by ion implantation in n- and p-type 4H-SiC

2009 ◽  
Vol 106 (1) ◽  
pp. 013719 ◽  
Author(s):  
Koutarou Kawahara ◽  
Giovanni Alfieri ◽  
Tsunenobu Kimoto
Keyword(s):  
Ion Implantation ◽  
Deep Levels ◽  
P Type

scholarly journals Reduction of deep levels generated by ion implantation into n- and p-type 4H–SiC

2010 ◽  
Vol 108 (3) ◽  
pp. 033706 ◽  
Author(s):  
Koutarou Kawahara ◽  
Jun Suda ◽  
Gerhard Pensl ◽  
Tsunenobu Kimoto
Keyword(s):  
Ion Implantation ◽  
Deep Levels ◽  
P Type

P-type ZnO thin films achieved by N+ ion implantation through dynamic annealing process

2012 ◽  
Vol 101 (11) ◽  
pp. 112101 ◽  
Author(s):  
M. A. Myers ◽  
M. T. Myers ◽  
M. J. General ◽  
J. H. Lee ◽  
L. Shao ◽  
...  
Keyword(s):  
Thin Films ◽  
Ion Implantation ◽  
Annealing Process ◽  
Zno Thin Films ◽  
P Type

Growth, Doping, Device Development and Characterization of CVD Beta-SiC Epilayers on Si(100) and Alpha-SiC(0001)

1987 ◽  
Vol 97 ◽  
Author(s):  
H. Kong ◽  
H. J. Kim ◽  
J. A. Edmond ◽  
J. W. Palmour ◽  
J. Ryu ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Elevated Temperatures ◽  
Deep Level ◽  
Schottky Diodes ◽  
Free Carriers ◽  
Device Development ◽  
Post Annealing ◽  
P Type ◽  
Sic Films

ABSTRACTMonocrystalline β-SiC films have been chemically vapor deposited on Si(100) and c-SiC(0001) at 1660K-1823K and 0.1 MPa using SiH4 and C2H4 carried in H2. Films grown directly on Si(100) contained substantial concentrations of dislocations, stacking faults and antiphase boundaries (APB); those on α-SiC(0001) contained double positioning boundaries. Both the APBs and the double positioning boundaries were eliminated by using off-axis orientations of the respective substrates. Films produced on Si(100) have also been doped during growth and via ion implantation with B or Al (p-type) or P or N (n-type) at LN, room and elevated temperatures. Results from the former procedure showed the ionized dopant/total dopant concentration ratios for N, P, B and Al to be 0.1, 0.2, 0.002 and 0.01, respectively. The solubility limits of N, P and B at 1660K were determined to be ∼ 2E20, 1E18 and 8E18 cm−3, respectively; that of Al exceeds 2E19 cm−3. High temperature ion implantation coupled with dynamic and post annealing resulted in a markedly reduced defect concentration relative to that observed in similar research at the lower temperatures. Schottky diodes, p-n junctions, and MOSFET devices have been fabricated. The p-n junctions have the characteristics of insulators containing free carriers and deep level traps. The MOSFETs show very good I-V characteristics up to 673K, but have not been optimized.

TEM Characterization of Arsenic and Phosphorus Implanted Silicon Devices

1997 ◽  
Vol 3 (S2) ◽  
pp. 467-468
Author(s):  
Lancy Tsung ◽  
Hun-Lian Tsai ◽  
Alwin Tsao ◽  
Makoto Takemura
Keyword(s):  
Ion Implantation ◽  
Crystalline Silicon ◽  
Source Region ◽  
Amorphous Layer ◽  
Common Source ◽  
Silicon Devices ◽  
Similar Region ◽  
Before And After ◽  
P Type ◽  
Silicon Device

Ion implantation of arsenic and phosphorus is a common practice in silicon devices for the formation of transistor source/drain regions. We used a TEM equipped with EDX capabilities to investigate effects of ion implantation in actual devices before and after annealing. A 200 kev field emission gun TEM was used in this study. Two implant cases were studied here. Both samples are p-type, (100) Si wafers.Figure 1 shows the microstructure in a common source region of a silicon device after being implanted by phosphorus (4x1014 cm−2 at 30 kv, 0°), while Figure 2 shows a similar region for arsenic implantation (5x1015 cm−2 at 45 kv, 0°). No screen layer was used during implantation. The phosphorus implant results in a ˜0.05 μm amorphous layer sandwiched between heavily damaged crystalline silicon. High resolution images reveal a rough amorphous/damaged crystalline boundary and high density defects due to silicon lattice displacements.

(Invited) P-Type and N-Type Channeling Ion Implantation of SiC and Implications for Device Design and Fabrication

2020 ◽  
Vol MA2020-02 (26) ◽  
pp. 1839-1839
Author(s):  
Hrishikesh Das ◽  
Swapna Sunkari ◽  
Joshua Justice ◽  
Roman Malousek ◽  
Jan Chochol ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Device Design ◽  
P Type

Development and Investigation on EBAS-100 of 100 mm Diameter Wafer for 4H-SiC Post Ion Implantation Annealing

2006 ◽  
Vol 527-529 ◽  
pp. 807-810 ◽  
Author(s):  
Masami Shibagaki ◽  
Masataka Satoh ◽  
Yasumi Kurematsu ◽  
Kenji Numajiri ◽  
Fumio Watanabe ◽  
...  
Keyword(s):  
Heat Capacity ◽  
Ion Implantation ◽  
Thermal Process ◽  
Electrical Power ◽  
Mean Square ◽  
Rapid Thermal Process ◽  
Volume Production ◽  
Electrical Power Consumption ◽  
P Type ◽  
Sic Wafer

We developed EBAS-100, which is available to 100 mm diameter SiC wafer, for post ion implantation annealing in order to realize silicon carbide (SiC) device with large volume production. EBAS-100 is able to perform the rapid thermal process due to the vacuum thermal insulation and small heat capacity of susceptor. Electrical power consumption density was 18.8 Wh/cm2 for EBAS-100, which is one-third smaller than that of our previous system (EBAS-50). Samples used in this study were p-type epitaxial 4H-SiC (0001) grown on 8o off SiC substrate. P+ ions (total dose; 2.0 x 1016 /cm2, thickness; 350 nm) were implanted into SiC samples at 500 oC. The root-mean-square (RMS) of surface roughness is estimated to be 0.21 nm for the sample annealed at 1700 oC for 5 min, which is much smooth than that of the sample annealed by the conventional RF inductive annealing (RMS value: 5.97 nm). Averaged sheet resistance (RS) value of 63.3 ohm/sq. is obtained with the excellent non-uniformity of RS (+/- 1.4 %) for the diameter of 76.0 mm.

Ion Implantation For High Performance Ill-V Jfets And Hfets

1996 ◽  
Vol 421 ◽  
Author(s):  
J. C. Zolper ◽  
A. G. Baca ◽  
M. E. Sherwin ◽  
J. F. Klem
Keyword(s):  
Ion Implantation ◽  
Conduction Band ◽  
Density Of States ◽  
High Performance ◽  
Electronic Devices ◽  
Semiconductor Materials ◽  
Comprehensive Treatment ◽  
Enabling Technology ◽  
Deep Donor ◽  
P Type

AbstractIon implantation has been an enabling technology for the realization of many high performance electronic devices in III-V semiconductor materials. We report on advances in ion implantation processing technology for application to GaAs JFETs, AlGaAs/GaAs HFETs, and InGaP or InA1P-barrier HFETs. In particular, the GaAs JFET has required the development of shallow p-type implants using Zn or Cd with junction depths down to 35 nm after the activation anneal. Implant activation and ionization issues for AlGaAs will be reported along with those for InGaP and InAlP. A comprehensive treatment of Si-implant doping of AlGaAs is given based on the donor ionization energies and conduction band density-of-states dependence on Al-composition. Si and Si+P implants in InGaP are shown to achieve higher electron concentrations than for similar implants in AlGaAs due to the absence of the deep donor (DX) level. An optimized P co-implantation scheme in InGaP is shown to increase the implanted donor saturation level by 65%.

Sign in / Sign up

Export Citation Format

Share Document