NOVEL CALCULATIONS IN THE FIELD OF ACCURATE ANALYTICAL MOS TRANSISTOR MODELLING

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

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Numerical modeling of MOS transistor with interconnections using lumped element-FDTD method

Microelectronics Journal ◽

10.1016/j.mejo.2012.10.005 ◽

2012 ◽

Vol 43 (12) ◽

pp. 995-1002

Author(s):

Samir Labiod ◽

Saida Latreche ◽

Christian Gontrand

Keyword(s):

Numerical Modeling ◽

Fdtd Method ◽

Mos Transistor ◽

Lumped Element

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Inertial sensing MEMS device using a floating-gate MOS transistor as transducer by means of modifying the capacitance associated to the floating gate

Microsystem Technologies ◽

10.1007/s00542-017-3647-7 ◽

2017 ◽

Vol 24 (6) ◽

pp. 2753-2764 ◽

Cited By ~ 6

Author(s):

G. S. Abarca-Jiménez ◽

J. Mares-Carreño ◽

M. A. Reyes-Barranca ◽

B. Granados-Rojas ◽

S. Mendoza-Acevedo ◽

...

Keyword(s):

Floating Gate ◽

Inertial Sensing ◽

Mos Transistor ◽

Mems Device

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Effect of Technology Scaling on MOS Transistor Performance with High-K Gate Dielectrics

MRS Proceedings ◽

10.1557/proc-716-b3.3 ◽

2002 ◽

Vol 716 ◽

Author(s):

Nihar R. Mohapatra ◽

Madhav P. Desai ◽

Siva G. Narendra ◽

V. Ramgopal Rao

Keyword(s):

Gate Dielectric ◽

Gate Dielectrics ◽

Channel Length ◽

Mos Transistors ◽

Short Channel ◽

Technology Scaling ◽

Mos Transistor ◽

Wide Range ◽

Impact Of Technology ◽

The Impact

AbstractThe impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.

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