On-chip gate delay variability measurement in scaled technology node

2016 ◽  
pp. 35-70
Author(s):  
Das ◽  
Amrutur ◽  
Onodera
Keyword(s):  
Gate Delay ◽  
Technology Node ◽  
Delay Variability ◽  
On Chip

Power Efficient and Improved Noise Margin of Sram Cell for System on Chip Applications

2018 ◽  
Author(s):  
Sunil Kumar Ojha ◽  
O.P. Singh ◽  
G.R. Mishra ◽  
P.R. Vaya
Keyword(s):  
Major Part ◽  
System On Chip ◽  
Process Technology ◽  
Power Efficient ◽  
Technology Node ◽  
Noise Margin ◽  
Sram Cell ◽  
On Chip ◽  
Margin Analysis

Noise margin analysis of SRAM cell is became more crucial for on chip applications. Currently the technology is migrating towards less than 10nm node and hence it is necessary to measure the noise margin of SRAM cell very effectively, since memory is one of the major part of system on chips (SOCs) and Network on chips (NOCs) devices. If the margin is not calculated efficiently then it may leads to bad chip product and the whole device which contains this chip may not work as per the expectation. This further leads to low yield which increases the number of defective chips compared to good one. In this paper the noise margin analysis of SRAM cell is performed using 7nm process technology node using HSPICE simulator.

scholarly journals Analytical Gate Delay Variation Model with Temperature Effects in Near-Threshold Region Based on Log-Skew-Normal Distribution

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 501
Author(s):  
Jingjing Guo ◽  
Peng Cao ◽  
Jiangping Wu ◽  
Zhiyuan Liu ◽  
Jun Yang
Keyword(s):  
Normal Distribution ◽  
Temperature Effects ◽  
Threshold Region ◽  
Gate Delay ◽  
Skew Normal Distribution ◽  
Delay Variability ◽  
Delay Variation ◽  
Skew Normal ◽  
Variation Model ◽  
Near Threshold

The near-threshold design is widely employed in the energy-efficient circuits, but it suffers from a high sensitivity to process variation, which leads to 2X delay variation due to temperature effects. Hence, it is not negligible. In this paper, we propose an analytical model for gate delay variation considering temperature effects in the near-threshold region. The delay variation model is constructed based on the log-skew-normal distribution by moment matching. Moreover, to deal with complex gates, a multi-variate threshold voltage approximation approach of stacked transistors is proposed. Also, three delay metrics (delay variability, ± 3 σ percentile points) are quantified and have a comparison with other known works. Experimental results show that the maximum of delay variability is 5% compared with Monte Carlo simulation and improves 5X in stacked gates compared with lognormal distribution. Additionally, it is worth mentioning that, the proposed model exhibits excellent advantages on − 3 σ and stacked gates, which improves 5X–10X in accuracy compared with other works.

Analysis of a Media Processor Functional Failure

2009 ◽  
Author(s):  
Alan Putman
Keyword(s):  
Failure Rate ◽  
Basic Function ◽  
System On Chip ◽  
Functional Failure ◽  
Technology Node ◽  
Media Processor ◽  
N Doping ◽  
Cause Of Failure ◽  
On Chip

Abstract A system-on-chip processor (90 nm technology node) was experiencing a high basic function failure rate. Using a lab-based production tester, laser assisted device alteration, nanoprobing, and physical inspection; the cause of failure was traced to a single faulty P channel transistor. The transistor had been partially subjected to N doping due to poor photo-resist coverage caused by halation.

Gate Delay Variability due to Random Telegraph Noise

2021 ◽  
Author(s):  
Rodolfo G. Barbosa ◽  
Thiago H. Both ◽  
Gilson Wirth
Keyword(s):  
Gate Delay ◽  
Random Telegraph Noise ◽  
Telegraph Noise ◽  
Delay Variability

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

2009 ◽  
Vol 22 (2) ◽  
pp. 256-267 ◽  
Author(s):  
Bishnu Prasad Das ◽  
Bharadwaj Amrutur ◽  
H. S. Jamadagni ◽  
N. V. Arvind ◽  
V. Visvanathan
Keyword(s):  
Ring Oscillator ◽  
Gate Delay ◽  
Delay Variability
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