Switching activity reduction in embedded systems: a genetic bus encoding approach

2005 ◽  
Vol 152 (6) ◽  
pp. 756 ◽  
Author(s):  
G. Ascia ◽  
V. Catania ◽  
M. Palesi ◽  
A. Parlato
Keyword(s):  
Embedded Systems ◽  
Switching Activity ◽  
Bus Encoding ◽  
Switching Activity Reduction

scholarly journals High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

2010 ◽  
Vol E93-D (1) ◽  
pp. 2-9
Author(s):  
Kohei MIYASE ◽  
Xiaoqing WEN ◽  
Hiroshi FURUKAWA ◽  
Yuta YAMATO ◽  
Seiji KAJIHARA ◽  
...  
Keyword(s):  
Switching Activity ◽  
Clock Gating ◽  
Scan Testing ◽  
Switching Activity Reduction

scholarly journals A New Method for Low Power Design of Two-Level Logic Circuits

VLSI Design ◽  
1999 ◽  
Vol 9 (2) ◽  
pp. 147-157
Author(s):  
G. Theodoridis ◽  
S. Theoharis ◽  
D. Soudris ◽  
C. Goutis
Keyword(s):  
Low Power Design ◽  
Logic Circuits ◽  
New Method ◽  
Covering Problem ◽  
Switching Activity ◽  
Network Nodes ◽  
Input Signals ◽  
Input Variables ◽  
Comparison Of The Results ◽  
Switching Activity Reduction

A new method for implementing two-level logic circuits, which exhibit minimal power dissipation, is introduced. Switching activity reduction of the logic network nodes is achieved by adding extra input signals to specific gates. Employing the statistic properties of the primary inputs, a new concept for grouping the input variables with similar features is introduced. Appropriate input variables are chosen for reducing the switching activity of a logic circuit. For that purpose, an efficient synthesis algorithm, which generates the set of all groups of the variables and solves the minimum covering problem for each group is developed. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a substantial power reduction can be achieved.

scholarly journals A CLASS OF IRREDUNDANT ENCODING TECHNIQUES FOR REDUCING BUS POWER

2002 ◽  
Vol 11 (05) ◽  
pp. 445-457 ◽  
Author(s):  
YAZDAN AGHAGHIRI ◽  
FARZAN FALLAH ◽  
MASSOUD PEDRAM
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Total Power ◽  
Switching Activity ◽  
Printed Circuit ◽  
Memory Address ◽  
Total Power Consumption ◽  
Bus Encoding

This paper proposes a number of encoding techniques for decreasing power dissipation on global buses. The best target for these techniques is a wide and highly capacitive memory bus. Switching activity of the bus is reduced by means of encoding the values that are conveyed over them. More precisely, three irredundant bus-encoding techniques are presented in this paper. These techniques decrease the bus activity by as much as 86% for instruction addresses without the need to add redundant bus lines. Having no redundancy means that exercising these techniques on any existing system does not require redesign and remanufacturing of the printed circuit board of the system. The power dissipation of the encoder and decoder blocks is insignificant in comparison with the power saved on the memory address bus. This makes these techniques capable of reducing the total power consumption.

Instruction Format Design for Low Power Embedded Systems

2015 ◽  
Vol 789-790 ◽  
pp. 829-832
Author(s):  
Jong Hee M. Youn ◽  
Dae Jin Park ◽  
Jeong Hun Cho ◽  
Doo San Cho
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Digital Circuit ◽  
Total Power ◽  
Switching Activity ◽  
Design Constraint ◽  
Instruction Fetch ◽  
Total Power Consumption ◽  
Instruction Format

Embedded systems demand to take high performance while executing on batteries. In such environment, the systems must be optimized with available technique to reduce energy consumption while not sacrificing performance. Especially, in mobile devices, power consumption is an important design constraint. Switching activity accounts for over 90% of total power consumption in a digital circuit. In this paper, we describe an approach to design instruction format for low power instruction fetch. The proposed method reduces switching activity of the instruction fetch logic by using a heuristic that minimizes switching between adjacent instructions. To do this, the proposed approach encodes opcodes so that frequently executed instruction pairs have smaller bit changes.

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