Scan chain ordering technique for switching activity reduction during scan test

2005 ◽  
Vol 152 (5) ◽  
pp. 609 ◽  
Author(s):  
W.-D. Tseng
Keyword(s):  
Switching Activity ◽  
Scan Test ◽  
Scan Chain ◽  
Switching Activity Reduction ◽  
Chain Ordering

scholarly journals Scan Chain Ordering to Reduce Test Data for BIST-Aided Scan Test Using Compatible Scan Flip-Flops

2010 ◽  
Vol E93-D (1) ◽  
pp. 10-16 ◽  
Author(s):  
Hiroyuki YOTSUYANAGI ◽  
Masayuki YAMAMOTO ◽  
Masaki HASHIZUME
Keyword(s):  
Test Data ◽  
Scan Test ◽  
Scan Chain ◽  
Chain Ordering

Efficient Low-power Scan Test Method based on Exclusive Scan and Scan Chain Reordering

2020 ◽  
Vol 20 (4) ◽  
pp. 390-404
Author(s):  
Dooyoung Kim ◽  
Jinuk Kim ◽  
Muhammad Ibtesam ◽  
Umair Saeed Solangi ◽  
Sungju Park
Keyword(s):  
Low Power ◽  
Test Method ◽  
Scan Test ◽  
Scan Chain

scholarly journals High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme

2010 ◽  
Vol E93-D (1) ◽  
pp. 2-9
Author(s):  
Kohei MIYASE ◽  
Xiaoqing WEN ◽  
Hiroshi FURUKAWA ◽  
Yuta YAMATO ◽  
Seiji KAJIHARA ◽  
...  
Keyword(s):  
Switching Activity ◽  
Clock Gating ◽  
Scan Testing ◽  
Switching Activity Reduction

scholarly journals A New Method for Low Power Design of Two-Level Logic Circuits

VLSI Design ◽  
1999 ◽  
Vol 9 (2) ◽  
pp. 147-157
Author(s):  
G. Theodoridis ◽  
S. Theoharis ◽  
D. Soudris ◽  
C. Goutis
Keyword(s):  
Low Power Design ◽  
Logic Circuits ◽  
New Method ◽  
Covering Problem ◽  
Switching Activity ◽  
Network Nodes ◽  
Input Signals ◽  
Input Variables ◽  
Comparison Of The Results ◽  
Switching Activity Reduction

A new method for implementing two-level logic circuits, which exhibit minimal power dissipation, is introduced. Switching activity reduction of the logic network nodes is achieved by adding extra input signals to specific gates. Employing the statistic properties of the primary inputs, a new concept for grouping the input variables with similar features is introduced. Appropriate input variables are chosen for reducing the switching activity of a logic circuit. For that purpose, an efficient synthesis algorithm, which generates the set of all groups of the variables and solves the minimum covering problem for each group is developed. The comparison of the results, produced by the proposed method, and those from ESPRESSO shows that a substantial power reduction can be achieved.

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