Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction

P.-C. Tsai; S.-J. Wang

doi:10.1049/iet-cdt:20070115

Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction

IET Computers & Digital Techniques ◽

10.1049/iet-cdt:20070115 ◽

2008 ◽

Vol 2 (6) ◽

pp. 434 ◽

Cited By ~ 2

Author(s):

P.-C. Tsai ◽

S.-J. Wang

Keyword(s):

Test Data ◽

Test Time ◽

Test Time Reduction ◽

Time Reduction ◽

Scan Chain ◽

Multi Mode

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Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction

2006 15th Asian Test Symposium ◽

10.1109/ats.2006.261024 ◽

2006 ◽

Cited By ~ 7

Author(s):

Po-chang Tsai ◽

Sying-jyan Wang

Keyword(s):

Test Data ◽

Test Time ◽

Test Time Reduction ◽

Time Reduction ◽

Scan Chain ◽

Multi Mode

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Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture

16th Asian Test Symposium (ATS 2007) ◽

10.1109/ats.2007.33 ◽

2007 ◽

Author(s):

Sying-Jyan Wang ◽

Po-Chang Tsai ◽

Hung-Ming Weng ◽

Katherine Shu-Min Li

Keyword(s):

Test Data ◽

Test Time ◽

Test Time Reduction ◽

Time Reduction ◽

Multi Mode

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Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture

16th Asian Test Symposium (ATS 2007) ◽

10.1109/ats.2007.4387990 ◽

2007 ◽

Author(s):

Sying-Jyan Wang ◽

Po-Chang Tsai ◽

Hung-Ming Weng ◽

Katherine Shu-Min Li

Keyword(s):

Test Data ◽

Test Time ◽

Test Time Reduction ◽

Time Reduction ◽

Multi Mode

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Test data compression and test time reduction of longest-path-per-gate tests based on Illinois scan architecture

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197628 ◽

2003 ◽

Cited By ~ 7

Author(s):

M. Sharma ◽

J.H. Patel ◽

J. Rearick

Keyword(s):

Data Compression ◽

Test Data ◽

Test Time ◽

Test Data Compression ◽

Test Time Reduction ◽

Longest Path ◽

Time Reduction

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Test data compression and test time reduction using an embedded microprocessor

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2003.817140 ◽

2003 ◽

Vol 11 (5) ◽

pp. 853-862 ◽

Cited By ~ 8

Author(s):

Sungbae Hwang ◽

J.A. Abraham

Keyword(s):

Data Compression ◽

Test Data ◽

Test Time ◽

Test Data Compression ◽

Embedded Microprocessor ◽

Test Time Reduction ◽

Time Reduction

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Scan chain design for test time reduction in core-based ICs

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270) ◽

10.1109/test.1998.743185 ◽

2002 ◽

Cited By ~ 125

Author(s):

J. Aerts ◽

E.J. Marinissen

Keyword(s):

Test Time ◽

Design For Test ◽

Test Time Reduction ◽

Time Reduction ◽

Scan Chain ◽

Scan Chain Design

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Versuchszeit reduzieren - Möglichkeiten und Grenzen / Test Time Reduction - Chances and Limits

Materials Testing ◽

10.1515/mt-1998-400607 ◽

1998 ◽

Vol 40 (6) ◽

pp. 240-244

Author(s):

H Zenner

Keyword(s):

Test Time ◽

Test Time Reduction ◽

Time Reduction

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FPGA test time reduction through a novel interconnect testing scheme

Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02 ◽

10.1145/503048.503069 ◽

2002 ◽

Cited By ~ 8

Author(s):

Stuart McCracken ◽

Zeljko Zilic

Keyword(s):

Test Time ◽

Interconnect Testing ◽

Testing Scheme ◽

Test Time Reduction ◽

Time Reduction

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An efficient scan tree design for test time reduction

Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. ◽

10.1109/etsym.2004.1347657 ◽

2004 ◽

Cited By ~ 22

Author(s):

Y. Bonhomme ◽

T. Yoneda ◽

H. Fujiwara ◽

P. Girard

Keyword(s):

Test Time ◽

Design For Test ◽

Test Time Reduction ◽

Time Reduction

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2.2.1 Test time reduction by optimal test sequencing1

INCOSE International Symposium ◽

10.1002/j.2334-5837.2006.tb02741.x ◽

2006 ◽

Vol 16 (1) ◽

pp. 259-269 ◽

Cited By ~ 1

Author(s):

R. Boumen ◽

I.S.M. de Jong ◽

J.M. van de Mortel-Fronczak ◽

J.E. Rooda

Keyword(s):

Test Time ◽

Optimal Test ◽

Test Time Reduction ◽

Time Reduction

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