9.5 GHz GaInP/GaAs HBT divide-by-two frequency divider using super-dynamic D-type flip–flop technique

2007 ◽  
Vol 43 (13) ◽  
pp. 706 ◽  
Author(s):  
H.-J. Wei ◽  
C. Meng ◽  
Y.W. Chang ◽  
G.-W. Huang
Keyword(s):  
Frequency Divider ◽  
Flip Flop

scholarly journals A Broadband High-speed Programmable Multi-modulus Divider Based on CMOS Process

2021 ◽  
Vol 2132 (1) ◽  
pp. 012046
Author(s):  
Muzhen Hao ◽  
Xiaodong Liu ◽  
Zhizhe Liu ◽  
Feng Ji ◽  
Di Sun ◽  
...  
Keyword(s):  
Phase Noise ◽  
High Frequency ◽  
High Speed ◽  
Frequency Divider ◽  
Cmos Process ◽  
Frequency Division ◽  
Frequency Range ◽  
Flip Flop ◽  
Large Bandwidth ◽  
Level 2

Abstract This paper introduces a design of a high-speed programmable multi-modulus divider (MMD) based on 65nm CMOS process. The design adopts the cascade structure of 7 level 2/3 frequency dividers, and expands the frequency division range by adjusting the number of cascade stages, so as to achieve a continuous frequency division ratio of 16 to 255. Among them, the first level 2/3 frequency divider adopts the D flip-flop design of CML (current mode logic) structure, the second level 2/3 frequency divider adopts the D flip-flop design of E-TSPC (extended true-single-phase-clock) structure. The whole circuit realizes the working frequency range of 13∼18GHz high frequency and large bandwidth. This design has completed layout drawing and parasitic parameter extraction simulation. The simulation results show that the operating frequency range of the circuit can reach 13∼18GHz. When the input signal is 18GHz and the frequency division ratio is 255, the phase noise is about -135dBc/Hz@1kHz. It has the advantages of high frequency, large bandwidth, and low phase noise.

AlGaAs/GaAs HBT dynamic frequency divider constructed of a single d type flip-flop

1988 ◽  
Vol 24 (17) ◽  
pp. 1109 ◽  
Author(s):  
Y. Yamauchi ◽  
K. Nagata ◽  
O. Nakajima ◽  
H. Ito ◽  
T. Nittono ◽  
...  
Keyword(s):  
Frequency Divider ◽  
Flip Flop ◽  
Dynamic Frequency

A 36 GHz CIFF-TFF Dynamic Frequency Divider Using GaAs HBTs

2013 ◽  
Vol 441 ◽  
pp. 125-128
Author(s):  
Li Fan Wu
Keyword(s):  
High Speed ◽  
Heterojunction Bipolar Transistor ◽  
Frequency Divider ◽  
Schematic Diagram ◽  
60 Ghz ◽  
Flip Flop ◽  
Simulation Methodology ◽  
The Core ◽  
Core Part ◽  
Dynamic Frequency

A clock-inverter feed-forward toggle flip-flop (CIFF-TFF) based ultra-high-speed 2:1 dynamic frequency divider is designed in a GaAs heterojunction bipolar transistor (HBT) technology with fT of 60 GHz from Win Semiconductors corporation. The co-simulation methodology of electromagnetic field and schematic diagram is utilized in the design. Through tuning the currents in the core and the other parts of the divider separately, the dynamic frequency divider approaches an operating speed of 36 GHz with a power consumption of 162 mW in the core part from a single 6 V supply. The design is currently taped out.

scholarly journals A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2494
Author(s):  
Lu Tang ◽  
Kuidong Chen ◽  
Youming Zhang ◽  
Xusheng Tang ◽  
Changchun Zhang
Keyword(s):  
High Speed ◽  
Frequency Synthesizer ◽  
Phase Locked Loop ◽  
Frequency Divider ◽  
Flip Flop ◽  
Ka Band ◽  
Locking Range ◽  
Type Frequency ◽  
Operation Frequency ◽  
Programmable Frequency Divider

A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.

scholarly journals 40 GHz VCO and Frequency Divider in 28 nm FD-SOI CMOS Technology for Automotive Radar Sensors

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2114
Author(s):  
Giorgio Maiellaro ◽  
Giovanni Caruso ◽  
Salvatore Scaccianoce ◽  
Mauro Giacomini ◽  
Angelo Scuderi
Keyword(s):  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Frequency Divider ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Flip Flop ◽  
Frequency Dividers ◽  
Thermal Chamber ◽  
5 Ghz ◽  
28 Nm

This paper presents a 40 GHz voltage-controlled oscillator (VCO) and frequency divider chain fabricated in STMicroelectronics 28 nm ultrathin body and box (UTBB) fully depleted silicon-on-insulator (FD-SOI) complementary metal-oxide–semiconductor (CMOS) process with eight metal layers back-end-of-line (BEOL) option. VCOs architecture is based on an LC-tank with p-type metal-oxide–semiconductor (PMOS) cross-coupled transistors. VCOs exhibit a tuning range (TR) of 3.5 GHz by exploiting two continuous frequency tuning bands selectable via a single control bit. The measured phase noise (PN) at 38 GHz carrier frequency is −94.3 and −118 dBc/Hz at 1 and 10 MHz frequency offset, respectively. The high-frequency dividers, from 40 to 5 GHz, are made using three static CMOS current-mode logic (CML) Master-Slave D-type Flip-Flop stages. The whole divider factor is 2048. A CMOS toggle flip-flop architecture working at 5 GHz was adopted for low frequency dividers. The power dissipation of the VCO core and frequency divider chain are 18 and 27.8 mW from 1.8 and 1 V supply voltages, respectively. Circuit functionality and performance were proved at three junction temperatures (i.e., −40, 25, and 125 °C) using a thermal chamber.

scholarly journals All-optical Frequency Divider using TOAD based D-Flip-Flop

2021 ◽  
Vol 7 (01) ◽  
pp. 152-157
Author(s):  
Ashis Kumar Mandal
Keyword(s):  
Optical Communication ◽  
High Speed ◽  
Frequency Divider ◽  
Critical Parameters ◽  
Optical Frequency ◽  
Flip Flop ◽  
Light Pulses ◽  
Frequency Dividers ◽  
Communication Circuits ◽  
All Optical

From the last few decades the optical communication has been established as much easier process than electrical communication. Many optical proposed circuits have already been suggested in many fields in support of this. The optical communication circuits demand frequency dividers capable of operating well above 10 GHz. Here, an all-optical frequency divider using terahertz optical asymmetric demultiplexer (TOAD) based D-flip-flop is proposed in the optical domain in a configuration exactly like the standard electronic setup. It presents a high-speed flip-flop-based frequency divider incorporating a new high-speed latch topology with satisfactory performance. The proposed all-optical frequency division scheme has been theoretically demonstrated in this paper. In this scheme the input and output binary digits are expressed as the presence (1) and the absence (0) of the light pulses. The performance of this proposed optical realization is evaluated by numerical simulation that confirms its feasibility in terms of the choice of the critical parameters.

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