Low-power logic synthesis algorithm using multiple partitioning under delay constraints

Ick-Sung Choi; Sun-Young Hwang

doi:10.1049/el:19990409

Low-power logic synthesis algorithm using multiple partitioning under delay constraints

Electronics Letters ◽

10.1049/el:19990409 ◽

1999 ◽

Vol 35 (7) ◽

pp. 558 ◽

Cited By ~ 1

Author(s):

Ick-Sung Choi ◽

Sun-Young Hwang

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Synthesis Algorithm ◽

Delay Constraints ◽

Low Power Logic

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Low power logic synthesis under a general delay model

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1145/280756.280900 ◽

1998 ◽

Cited By ~ 8

Author(s):

Unni Narayanan ◽

Peichen Pan ◽

C. L. Liu

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Delay Model ◽

Low Power Logic

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Low power logic synthesis under a general delay model

Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379) ◽

10.1109/lpe.1998.708190 ◽

2002 ◽

Author(s):

U. Narayanan ◽

Peichen Pan ◽

C.L. Liu

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Delay Model ◽

Low Power Logic

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Low power logic synthesis for XOR based circuits

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97 ◽

10.1109/iccad.1997.643596 ◽

1997 ◽

Cited By ~ 1

Author(s):

Narayan ◽

Liu

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Low Power Logic

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Quantum Linear Logic Synthesis Algorithm Based on L-ESOP Reduction

Journal of Computer-Aided Design & Computer Graphics ◽

10.3724/sp.j.1089.2018.16567 ◽

2018 ◽

Vol 30 (8) ◽

pp. 1579

Author(s):

Lihua Wei ◽

Pengcheng Zhu ◽

Zhijin Guan

Keyword(s):

Linear Logic ◽

Logic Synthesis ◽

Synthesis Algorithm

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Partition Based Product Term Retiming for Reliable Low Power Logic Structure

Advances in Intelligent Systems and Computing - Advances in Information and Communication Networks ◽

10.1007/978-3-030-03402-3_13 ◽

2018 ◽

pp. 178-189

Author(s):

S. Jalaja ◽

A. M. Vijaya Prakash

Keyword(s):

Low Power ◽

Product Term ◽

Low Power Logic ◽

Logic Structure

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Selectively clocked skewed logic (SCSL): a robust low-power logic style for high-performance applications

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) ◽

10.1109/lpe.2001.945414 ◽

2002 ◽

Cited By ~ 3

Author(s):

N. Sirisantana ◽

A. Cao ◽

S. Davidson ◽

Cheng-Kok Koh ◽

K. Roy

Keyword(s):

Low Power ◽

High Performance ◽

Low Power Logic

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Opportunities and Challenges of Emerging Nanotechnologies for Future High-Speed and Low-Power Logic Applications

2005 IEEE Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2005.1635194 ◽

2006 ◽

Cited By ~ 2

Author(s):

R. Chau

Keyword(s):

Low Power ◽

High Speed ◽

Low Power Logic

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Novel III-N heterostructure devices for low-power logic and more

2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO) ◽

10.1109/nano.2016.7751336 ◽

2016 ◽

Cited By ~ 3

Author(s):

P. Fay ◽

W. Li ◽

L. Cao ◽

K. Pourang ◽

S. M. Islam ◽

...

Keyword(s):

Low Power ◽

Low Power Logic ◽

Heterostructure Devices

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High-Speed, Low-Power Logic ICs using Quasi-Normally-Off GaAs MESFETs

10.1109/esscirc.1980.5468776 ◽

1980 ◽

Author(s):

G. Nuzillat ◽

G. Bert ◽

F. Damay-Kavala ◽

C. Arnodo

Keyword(s):

Low Power ◽

High Speed ◽

Low Power Logic

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Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

IEEE Electron Device Letters ◽

10.1109/led.2008.2002945 ◽

2008 ◽

Vol 29 (10) ◽

pp. 1094-1097 ◽

Cited By ~ 58

Author(s):

G. Dewey ◽

M.K. Hudait ◽

Kangho Lee ◽

R. Pillarisetty ◽

W. Rachmady ◽

...

Keyword(s):

Quantum Well ◽

Low Power ◽

High Speed ◽

Carrier Transport ◽

High Mobility ◽

Performance Impact ◽

And Performance ◽

Low Power Logic

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