High-speed operation of resonant tunnelling flip-flop circuit employing MOBILE (monostable-bistable transition logic element)

1997 ◽  
Vol 33 (20) ◽  
pp. 1733 ◽  
Author(s):  
K. Maezawa ◽  
H. Matsuzaki ◽  
K. Arai ◽  
T. Otsuji ◽  
M. Yamamoto
Keyword(s):  
High Speed ◽  
Logic Element ◽  
Flip Flop ◽  
Resonant Tunnelling

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Dynamic Differential Flip-Flop without Explicit Output Latching Stage for High-Speed SoC

2021 ◽  
Author(s):  
Min-su Kim ◽  
Wonhyun Choi ◽  
Jong-Woo Kim ◽  
Chunghee Kim ◽  
Jae-Hyuk Oh ◽  
...  
Keyword(s):  
High Speed ◽  
Flip Flop

scholarly journals Novel explicit pulse-based flip-flop for high speed and low power SoCs

2007 ◽  
Vol 4 (23) ◽  
pp. 731-737 ◽  
Author(s):  
Sung-Chan Kang ◽  
Byung-Hwa Jung ◽  
Bai-Sun Kong
Keyword(s):  
Low Power ◽  
High Speed ◽  
Flip Flop

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

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