High performance antifuse with planar double dielectrics on Si1-xGex pad for field programmable gate array applications

1996 ◽  
Vol 32 (24) ◽  
pp. 2276 ◽  
Author(s):  
J. Kim ◽  
M.Y. Park ◽  
Y.H. Song ◽  
J.T. Baek
Keyword(s):  
Field Programmable Gate Array ◽  
High Performance ◽  
Field Programmable ◽  
Gate Array

scholarly journals Experimental Investigation on the Performances of a Multilevel Inverter Using a Field Programmable Gate Array-Based Control System

Energies ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 1016 ◽  
Author(s):  
Guido Ala ◽  
Massimo Caruso ◽  
Rosario Miceli ◽  
Filippo Pellitteri ◽  
Giuseppe Schettino ◽  
...  
Keyword(s):  
Experimental Investigation ◽  
Field Programmable Gate Array ◽  
High Performance ◽  
Multilevel Inverter ◽  
Experimental Results ◽  
Digital Controllers ◽  
Field Programmable ◽  
Gate Array ◽  
High Flexibility ◽  
Valid Solution

The Field Programmable Gate Array (FPGA) represents a valid solution for the design of control systems for inverters adopted in many industry applications, because of both its high flexibility of use and its high-performance with respect to other types of digital controllers. In this context, this paper presents an experimental investigation on the harmonic content of the voltages produced by a three-phase, five level cascaded H-Bridge Multilevel inverter with an FPGA-based control board, aiming also to evaluate the performance of the FPGA through the implementation of the main common modulation techniques and the comparison between simulation and experimental results. The control algorithms are implemented by means of the VHDL programming language. The output voltage waveforms, which have been obtained by applying to the inverter the main PWM techniques, are compared in terms of THD%. Simulation and experimental results are analyzed, compared and finally discussed.

scholarly journals A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 308
Author(s):  
Mojtaba Parsakordasiabi ◽  
Ion Vornicu ◽  
Ángel Rodríguez-Vázquez ◽  
Ricardo Carmona-Galán
Keyword(s):  
Field Programmable Gate Array ◽  
High Performance ◽  
Delay Line ◽  
Time Of Flight ◽  
Experimental Results ◽  
Digital Converter ◽  
Input Stage ◽  
Online Calibration ◽  
Field Programmable ◽  
Gate Array

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.

scholarly journals AN EFFECTIVE APPROACH OF BILATERAL FILTER IMPLEMENTATION IN SPARTAN-3 FIELD PROGRAMMABLE GATE ARRAY

2013 ◽  
pp. 17-20
Author(s):  
P. KARTHIKEYAN ◽  
M. GAUTHAM ◽  
R. RAMAKRISHNAN ◽  
A. MOOKKAIYA
Keyword(s):  
Field Programmable Gate Array ◽  
High Performance ◽  
Large Scale ◽  
Vlsi Architecture ◽  
Cost Effective ◽  
Bilateral Filter ◽  
Bilateral Filtering ◽  
High Resource ◽  
Field Programmable ◽  
Gate Array

This paper presents the Field Programmable Gate Array (FPGA) implementation of Bilateral Filter, in order to achieve high performance and low power consumption. Bilateral filtering is a technique to smooth images while preserving edges by means of a nonlinear combination of nearby image values. This method is nonlinear, local, and simple. We give an idea that bilateral filtering can be accelerated by bilateral grid scheme that enables fast edge-aware image processing. Nowadays, most of the applications require real time hardware systems with large computing potentiality for which fast and dedicated Very Large Scale Integration (VLSI) architecture appears to be the best possible solution. While it ensures high resource utilization, that too in cost effective platforms like FPGA, designing such architecture does offers some flexibilities like speeding up the computation by adapting more pipelined structures and parallel processing possibilities of reduced memory consumptions. Here we have developed an effective approach of bilateral filter implementation in Spartan-3 FPGA.

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